Method of fabricating a self-aligned double recess gate profile

Details Method of fabricating a self-aligned double recess gate profile Method of fabricating a self-aligned double recess gate profile

1995-05-30

1996-09-17

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437203, 437912, H01L 218258

Patent

active

055567975

ABSTRACT:
A method of fabricating a self-aligned double gate recess profile in a semiconductor substrate is disclosed in which a first mask layer is formed over the substrate. A second mask layer having an opening is formed over the first mask layer. An opening at least as wide as the second mask layer's opening is formed through the first mask layer to expose the substrate beneath the second mask layer's opening. A first recess is etched in the semiconductor through the second mask layer's opening. The first mask layer's opening is then uniformly expanded and a wider recess, aligned to the first recess, is then formed in the semiconductor. The method is particularly applicable to the formation of self-aligned gate and channel recesses in a GaAs MESFET.

REFERENCES:
patent: 4616400 (1986-10-01), Macksey
patent: 5270228 (1993-12-01), Ishikawa
patent: 5364816 (1994-11-01), Boos
DiLorenzo, ed., "GaAs FET Principles and Technology," Artech House, Inc. 1982, pp. 286-289.
Williams, "Gallium Arsenide Processing Techniques," Artech House, Inc., 1984, pp. 69-70.
Hudgens et al. "Process Control of the Spacing Between the Gate and Gate Recess for GaAs MESFETs," 1994 U.S. Conference on GaAs Manufacturing Technology, pp. 45-48.

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