Method of fabricating a self-aligned contact hole for a semicond

Details Method of fabricating a self-aligned contact hole for a semicond Method of fabricating a self-aligned contact hole for a semicond

1996-02-26

1998-03-17

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437203, 437228, 437235, 437195, H01L 21265

Patent

active

057285950

ABSTRACT:
A plurality of gate electrodes are formed over a semiconductor substrate. An etching stopper layer is formed on these plurality of gate electrodes. Sidewall layers are formed on the side faces of the plurality of gate electrodes. An interlayer insulating film covering the plurality of gate electrodes and the sidewall layers is formed. A contact hole is formed in the interlayer insulating film among the plurality of gate electrodes. Here, the contact hole is formed in the interlayer insulating film by making the etching rate of the etching stopper film lower than the etching rate of the interlayer insulating film and the etching rate of the sidewall layer substantially equivalent to or higher than the etching rate of the interlayer insulating film.

REFERENCES:
patent: 5135881 (1992-08-01), Saeki
patent: 5296400 (1994-03-01), Park et al.
patent: 5399532 (1995-03-01), Lee et al.
patent: 5482894 (1996-01-01), Havemann
patent: 5550071 (1996-08-01), Ryou
patent: 5580811 (1996-12-01), Kim

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