Method of fabricating a PbS-PbSe IR detector array

Details Method of fabricating a PbS-PbSe IR detector array Method of fabricating a PbS-PbSe IR detector array

1986-03-12

1987-08-25

Smith, John D.

Coating processes

Electrical product produced

Photoelectric

437228, B05D 512

Patent

active

046892460

ABSTRACT:
A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

REFERENCES:
patent: 2809132 (1957-10-01), Bloem
patent: 2997409 (1961-08-01), McLean
patent: 3121023 (1964-02-01), Spencer
patent: 3178312 (1965-04-01), Johnson
patent: 4427713 (1984-01-01), White
patent: 4602158 (1986-07-01), Barrett
patent: 4617608 (1986-10-01), Blonder

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