Metal fusion bonding – Process – Plural joints
Patent
1993-07-27
1994-09-13
Ramsey, Kenneth J.
Metal fusion bonding
Process
Plural joints
228175, 29830, H05K 336
Patent
active
053461177
ABSTRACT:
Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.
REFERENCES:
patent: 5031308 (1991-07-01), Yamashita et al.
patent: 5147210 (1992-09-01), Patterson et al.
Kohn Harold
Lazzarini Donald J.
Goldman Richard M.
International Business Machines - Corporation
Ramsey Kenneth J.
LandOfFree
Method of fabricating a parallel processor package does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a parallel processor package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a parallel processor package will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1114864