Method of fabricating a non-volatile memory device

Details Method of fabricating a non-volatile memory device Method of fabricating a non-volatile memory device

2001-11-26

2002-12-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000, C257S315000, C257S314000

Reexamination Certificate

active

06495467

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-08131, filed on Feb. 19, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a non-volatile memory device having a floating gate.
BACKGROUND OF THE INVENTION
Non-volatile memory devices can retain their previous data even though their power supplies are interrupted. Non-volatile memory devices include EPROMs capable of being electrically programmed and erased through the irradiation of a UV light and EEPROMs capable of being electrically programmed and erased. Flash memories have a small chip size and excellent program and erase characteristics in the EEPROM.
The non-volatile memory device typically includes a floating gate capable of accumulating electric charges in a general MOS transistor structure. A thin gate oxide layer called a tunnel oxide layer is interposed on a semiconductor substrate to form a floating gate. A gate interlayer dielectric layer is interposed on an upper portion of the floating gate to form a control gate electrode. Therefore, the floating gate is electrically insulated from the semiconductor substrate and the control gate electrode by the tunnel oxide layer and the gate interlayer dielectric layer.
The above-stated data program method of a non-volatile memory device includes a method using Fowler-Nordheim(FN) tunneling or a method using hot electron injection. In the method using FN tunneling, a high voltage is applied to a control gate electrode of the non-volatile memory to apply a high electric field to a tunnel oxide layer, and electrons of a semiconductor substrate pass the tunnel oxide layer and are injected into a floating gate by the high electric field. In the method of hot electron injection, a high voltage is applied to a control gate electrode and a drain region of a non-volatile memory to inject a hot electron generated near the drain region to a floating gate through a tunnel oxide layer. Therefore, a high electric field should be applied to the tunnel oxide layer in both FN tunneling and hot electron injection. In this case, a high coupling ratio is required in order to apply a high electric field to the tunnel oxide layer. The coupling ratio(C
R
) is shown in the following formula.
C
R
=C
ono
/C
tun
+C
ono
  [formula 1]
In this case C
ono
indicates capacitance between a control gate electrode and a floating gate, C
tun
indicates capacitance applied to the tunnel oxide layer interposed between the floating gate and the semiconductor substrate. Therefore, the surface area of the floating gate overlapped with the control gate electrode should be increased in order to increase the coupling ratio(C
R
). However, when increasing the surface area of the floating gate, it is difficult to increase the integration degree of a non-volatile memory device.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of fabricating a non-volatile memory device having a floating gate, which can increase an integration degree of the device and obtain high capacitance of a gate interlayer dielectric layer.
These and other objects, advantages and features of the present invention may be provided by a method of fabricating a non-volatile memory device, where a floating gate has a U-shape thereby widening a size of a gate interlayer dielectric layer between the floating gate and a control gate electrode.
According to one aspect of the present invention, a method of forming a non-volatile memory device includes forming a device isolation layer in a predetermined region of a semiconductor substrate, thereby defining at least one active region. A floating gate pattern covering the active regions and having a gap region exposing the device isolation layer between the active regions is formed. An insulation material pattern where the width of a projection is wider than an upper width of the gap region while the projection covers the gap region and is higher than an upper surface of the floating gate pattern is formed. The floating gate pattern is etched using the insulation material pattern as etching mask, thereby forming a modified floating gate pattern having a U-shaped cross section on an active region. The insulation material pattern is removed, and a gate interlayer dielectric layer and a control gate electrode layer are sequentially formed on a surface of the semiconductor substrate where the insulation material pattern is removed.
It is preferable that the floating gate pattern be formed with a lower floating gate pattern, formed by interposing a tunnel oxide layer on the active regions simultaneously forming the device isolation layer, and an upper floating gate pattern, deposited on an upper portion of the lower floating gate pattern.
In one embodiment, the method of forming the floating gate pattern includes forming a tunnel oxide layer, a lower floating gate layer and a CMP stopping layer on a semiconductor substrate. The CMP stopping layer, lower floating gate layer, tunnel oxide layer and semiconductor substrate are sequentially patterned, thereby forming a trench region and defining at least one active region. A device isolation layer filling the trench region is formed, then the CMP stopping layer is removed, thereby forming a device isolation layer filling the trench region and a lower floating gate pattern interposing a tunnel oxide layer on the active regions. An upper floating gate layer and a sacrificial insulation layer are sequentially formed on an entire surface of a semiconductor substrate where the floating gate pattern is formed. The sacrificial insulation layer and the floating gate layer are patterns, thereby forming a sacrificial insulation layer pattern and an upper floating gate pattern sequentially deposited by having a gap region covering the active regions and exposing the device isolation layer between the active regions. As a result, a floating gate pattern comprising the lower floating gate pattern and the upper floating gate pattern is formed on the active regions.
It is preferable that the insulation material pattern form a projection wider than the gap region by flowing a photosensitive layer filling the gap region between the floating gate pattern or forming a polymer material layer formed in a sidewall or an upper portion of the photosensitive layer. It is also preferable that the insulation material pattern be formed with an oxide layer having a spacer.
In one embodiment, the method of forming the insulation material pattern includes forming a photosensitive layer filling the gap region on a surface of the resultant structure where the floating gate pattern and the sacrificial insulation layer pattern are formed. An upper portion of the photosensitive layer is removed, thereby exposing an upper portion of the sacrificial insulation layer pattern and simultaneously forming a photosensitive pattern inside the gap region. The sacrificial insulation layer pattern is removed, thereby exposing the floating gate pattern on the active regions and forming the photosensitive pattern having a projection higher than an upper portion of the floating gate pattern. Lastly, the photosensitive layer pattern is flowed thereby forming a modified photosensitive layer pattern covering an edge of the floating gate pattern. In another method, a polymer material layer is formed on an upper portion and sidewall of the projection of the photosensitive layer pattern, thereby forming a modified photosensitive pattern covering an edge of the floating gate pattern.
Another method of forming the insulation material pattern includes forming an oxide layer filling the gap region on a surface of a semiconductor substrate where the floating gate pattern and the sacrificial insulation layer pattern are formed. The oxide layer is etched using an etching method, thereby exposing an upper portion of the sacrificial insulation la

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