Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-04-05
2001-11-13
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S723000, C438S724000, C438S733000
Reexamination Certificate
active
06316368
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of forming a node contact.
2. Description of the Related Art
A dynamic random access memory (DRAM) is a memory circuit that is most often used in computers and electronic products. Due to the development of the industry, there is a correspondingly greater need for high-capacity DRAM.
In a memory cell of a DRAM, a node contact is used to connect a capacitor and a transistor. The steps of forming the node contact include etching a dielectric layer on a substrate to form a node contact opening that exposes a part of the substrate, and filling the node contact opening with a conductive layer to form a conductive plug. In order to prevent electrical connection between the conductive plug and bit lines, the width of the conductive plug must be shorter than the distance between the bit lines. In this manner, a reserved tolerance window is obtained. When the node contact opening is patterned, the tolerance of the step needs to be within the range of the tolerance window so as to prevent the conductive plug from making contact with the bit lines. However, as the integration of semiconductor devices increases, the linewidth of the semiconductor devices is decreased. The limitation of the photolithography and etching process prevents the size of node contact opening from being further reduced. In a semiconductor fabrication process with a linewidth lower than 0.2 micrometers, the range of the tolerance window is especially insufficient when forming the node contact opening by the conventional method. This, in turn, causes the contact plug to make contact with the bit line and leads to shorts in devices.
There are two conventional methods to solve the above-described problems. The first method is to form an etching stop layer on the bit lines. During the step of etching the node contact opening, the etching stop layer prevents the bit lines from being etched. However, the method for forming the node contact opening is complicated and easily degrades the product quality. Thus, this method does not benefit the formation of the node contact opening.
Another method solves the problem by adjusting the etching parameters to form a node contact opening. The width of the node contact opening gradually decreases from the top to the bottom. Because the width of the node contact opening gradually decreases from the top to the bottom, the width of the node contact opening between the bit lines is shorter than the width at the surface of the dielectric layer. An electrical connection between the conductive plug and the bit lines does not occur. However, the increase in the width of the reserved tolerance window by this method is limited. The conductive plug still easily makes contact with the bit lines. The quality of the semiconductor devices formed by this method is still poor.
FIG. 1
is a schematic, cross-sectional view of a portion of a semiconductor device showing a conventional node contact.
Referring to
FIG. 1
, a substrate
100
including a gate
110
, a dielectric layer
102
, a bit line
106
, and a dielectric layer
104
is provided. The dielectric layers
102
and
104
are patterned. A trapezoidally cross-sectioned opening
112
is formed to expose a part of the substrate
100
. The width of the trapezoidally cross-sectioned opening
112
gradually decreases from the top to the bottom, which gives the profile of the opening
112
its trapezoidal shape. A conductive plug
114
is formed to fill the trapezoidally cross-sectioned opening
112
and cover a portion of the dielectric layer
104
, so as to form a node contact. The node contact formed by this method has smaller width between the bit lines
106
compared with a node contact formed from a vertical-sidewall opening, in order to prevent the node contact from making contact with the bit lines
106
. However the width reduction is not great, and thus a wider reserved tolerance window cannot be further provided. Device shorts caused by electrical connection between the conductive plug
114
of the node contact and the bit line
106
still occur.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a node contact opening. A dielectric layer is formed on a substrate. A first conductive layer is formed on the dielectric layer. Portions of the first conductive layer are removed until the dielectric layer is exposed to leave a remaining first conductive layer as a portion of the contact node. The dielectric layer beside the remaining first conductive layer comprising a cross-sectionally trapezoidal opening formed therein is exposed. The cross-sectionally trapezoidal opening is formed though the first conductive layer to expose a portion of the dielectric layer. A width of the cross-sectionally trapezoidal opening gradually decreases from top to bottom. A portion of the dielectric layer exposed by the cross-sectionally trapezoidal opening is removed to form a node contact opening in the dielectric layer until a part the substrate is exposed. A sidewall of the node contact opening is perpendicular to a surface of the substrate. A second conductive layer is formed on the remaining first conductive layer to fill the cross-sectionally trapezoidal opening and the node contact opening.
The present invention forms the cross-sectionally trapezoidal opening in the first conductive layer. The dielectric layer is etched with the remaining first conductive layer serving as an etching mask to form the node contact opening. In this manner, a reserved tolerance window with a wider range is obtained. Hence, the invention prevents electrical connection between the conductive plug and the bit lines and also prevents shorts in devices.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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patent: 5837577 (1998-11-01), Cherng
patent: 5893734 (1999-04-01), Jeng et al.
patent: 5895239 (1999-04-01), Jeng et al.
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patent: 6187626 (2001-02-01), Sze
patent: 6214727 (2001-04-01), Parekh
patent: 6255224 (2001-07-01), Kim
Chen Chieh-Te
Lin Kwang-Ming
Liu Pang-Miao
Peng Tzu-Min
Brown Charlotte A.
Huang Jiawei
J.C. Patents
United Microelectronics Corp.
Utech Benjamin L.
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