Method of fabricating a multi-layered printed wiring board

Details Method of fabricating a multi-layered printed wiring board Method of fabricating a multi-layered printed wiring board

1998-01-26

2000-09-19

Gorgos, Kathryn

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

205163, 205166, 205183, C25D 502, H05K 300

Patent

active

061206709

ABSTRACT:
There is provided a method of fabricating a multi-layered printed wiring board, including the steps of (a) forming a multi-layered substrate with a hole which will make a blind via-hole, (b) plating the multi-layered substrate, (c) forming an internal layer circuit pattern and an external layer circuit pattern, (d) laying one multi-layered substrate on another, (e) forming a product of the step (d) with a through-hole, (f) covering surfaces of a product of the step (e) including an inner wall surface of the through-hole with an electrically conductive film, (g) forming a resist in an area other than the through-hole, (h) plating the inner wall surface of the through-hole, (i) removing the resist, and (j) removing the electrically conductive film formed on the surfaces of the product of the step (e). The above-mentioned method makes it possible to shorten a time for plating an electrically conductive film from ten hours down to only one hour, avoid short-circuit caused by plating, and reduce fabrication costs by 30-50%.

REFERENCES:
patent: 5183552 (1993-02-01), Bressel et al.
patent: 5575898 (1996-11-01), Wolf et al.
patent: 5693209 (1997-12-01), Bressel et al.
patent: 5827386 (1998-10-01), Bhatt et al.
patent: 5840363 (1998-11-01), Rosch et al.
JPO English Abstract for JP408204339A, Aug. 9, 1996.

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