Method of fabricating a MOSFET with graded source and drain regi

Details Method of fabricating a MOSFET with graded source and drain regi Method of fabricating a MOSFET with graded source and drain regi

1986-11-04

1988-03-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 43, 437 44, 437147, 437154, 437157, 357 233, 357 239, 357 91, 148DIG53, 148DIG82, 148DIG106, H01L 21265

Patent

active

047286172

ABSTRACT:
A method of forming metal oxide semiconductor field-effect transistors (MOSFET) is described wherein the source and drain regions are disposed by ion implantation in a manner substantially perpendicular to the substrate surface in two steps, such that the concentration of impurities increases with lateral distance away from the gate electrode member to suppress the hot e injection, to prevent channeling effect, to increase punch through voltage and to increase gate-aided breakdown voltage.

REFERENCES:
patent: 4198250 (1980-04-01), Jecmen
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4536944 (1985-08-01), Bracco et al.
Ghandhi, VLSI Fabrication Principles, John Wiley and Sons, 1983.

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