Method of fabricating a MOS read-only semiconductor memory array

Details Method of fabricating a MOS read-only semiconductor memory array Method of fabricating a MOS read-only semiconductor memory array

1996-04-22

1998-03-31

Niebling, John

Fishing, trapping, and vermin destroying

437 45, H01L 21265

Patent

active

057337950

ABSTRACT:
A method is described for a read-only MOS semiconductor memory. An addressable array of a multiplicity of cells each comprising a single MOS transistor is coded for preselected cells by providing them with source/drain regions which are spaced apart from edges of their respective overlying gate electrode regions. This is accomplished by a masking step late in the fabrication sequence. In this way, a dense MOS memory having rapid manufacturing turn-around is provided.

REFERENCES:
patent: 5389565 (1995-02-01), Gyure et al.
patent: 5403764 (1995-04-01), Yamamoto et al.
patent: 5529942 (1996-06-01), Hong et al.

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