Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Incorporating resilient component
Reexamination Certificate
1998-08-26
2001-05-08
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Incorporating resilient component
C438S118000, C438S127000, C438S611000
Reexamination Certificate
active
06228686
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of making microelectronic assemblies, and to components for use in fabrication of microelectronic assemblies.
BACKGROUND OF THE INVENTION
Complex microelectronic devices such as modern semiconductor chips require numerous connections to other electronic components. For example, a complex microprocessor chip may require hundreds of connections to external devices.
As described in certain preferred embodiments of commonly assigned U.S. Pat. No. 5,148,265 and 5,148,266, a chip package may include a flexible sheetlike structure referred to as a “interposer” or “chip carrier” having terminals disposed on a flexible sheetlike structure. The interposer may be disposed on the front or contact bearing surface of the chip so that the terminals face away from the chip. The terminals are connected to contacts on the chip by flexible leads. Preferably, a compliant layer is disposed between the terminals and the chip. In certain preferred embodiments, the packaged chip occupies the same area, or only a slightly larger area than the chip itself. The packaged chip can be readily tested and can be mounted to a substrate such as a printed circuit board by bonding the terminals of the chip carrier to the contact pads of the substrate. In use, the terminals on the chip carrier are free to move relative to the chip. This allows the assembly to compensate for differential thermal expansion and warpage of the chip or substrate without imposing significant stresses on the bonds.
As taught in certain embodiments of commonly assigned U.S. Pat. No. 5,518,964, microelectronic assemblies incorporating flexible leads can be fabricated using a first element or connection component including a dielectric structure having leads on a bottom surface. Each such lead has a fixed end permanently attached to the dielectric structure and, typically, connected to one or more terminals on the top surface of the dielectric structure. Each such lead also has a free or tip end remote from the fixed or terminal end. Preferably, the free or tip ends of the leads are releasably attached to the dielectric structure. This element can be juxtaposed with a second microelectronic element such as a semiconductor chip or wafer, and the free ends of the leads may be bonded to contacts on such second microelectronic element. After bonding, the elements are moved vertically away from one another through a predetermined displacement, thereby detaching the free or tip ends of the leads from the bottom surface of the dielectric component and deforming the leads to a vertically extensive configuration. Preferably, a curable encapsulant is introduced between the elements and around the leads during or after the moving step, so as to provide a compliant layer between the dielectric layer and the second microelectronic element. This arrangement allows fabrication of compliant chip assemblies having advantages similar to those discussed above with respect to the '265 and '266 patents using a process which permits simultaneous connection and forming of numerous leads. In certain preferred embodiments according to the '964 patent, one of the microelectronic assemblies may include numerous semiconductor chips. For example, one microelectronic element may be a wafer incorporating numerous chips, and leads on all of the chips may be connected and formed in the same operations. After these operations, the resulting large assembly can be severed to form individual units each including one or more of the chips originally present in the wafer, together with a portion of the dielectric element and the terminals thereon.
In those embodiments of the '964 invention which use a pre-formed connection component with leads thereon, and which register the connection component with a wafer or other microelectronic device, the spacing between the leads on the component desirably is controlled precisely. This allows registration of the free ends of the leads with contacts on a wafer or other microelectronic device. For example, certain preferred embodiments disclosed in the '964 patent use a temporary reinforcing layer overlying the dielectric layer, and also use a rigid, ring-like frame to maintain the dielectric layer and the reinforcing layer to maintain the dielectric layer in tension. These features help to control thermal expansion and contraction of the connection component during the processes used to bond the free ends of the leads to the wafer or other microelectronic component, and help to maintain the desired spacing between the lead free ends.
Copending, commonly assigned U.S. patent application Ser. No. 08/989,312 discloses enhancements to processes taught in the '964 patent. Certain processes taught in the '312 application use a metallic conductive element. Leads are provided on a bottom surface of such element. Each lead has a fixed end permanently attached to the conductive element, and a free or tip end releasably attached to the conductive element. The conductive element with the leads thereon is juxtaposed with a microelectronic element such as a chip or wafer, and the tip ends of the leads are bonded to the contacts of the microelectronic element. The conductive element and microelectronic element are moved away from one another, thereby bending the leads into a vertically-extensive configuration, and a flowable material is injected and cured so as to form a dielectric layer around the leads. After formation of the dielectric layer, the conductive layer is etched or otherwise removed so as to leave portions of the conductive layer as individual terminals associated with the individual leads. In a variant of this process, each lead may have a pre-formed terminal of a first metal such as gold, provided at the juncture of the fixed end of the lead and the conductive layer before the lead-bonding and moving steps. The conductive layer is formed from a second metal, such as copper. When the conductive layer is etched away, the pre-formed terminals remain.
Preferred arrangements taught in copending, commonly assigned U.S. patent application Ser. Nos. 08/927,601 and 08/712,855 disclose curved lead configurations useful in the foregoing processes. Copending, commonly assigned U.S. patent application Ser. No. 08/989,582 discloses further improvements in such processes. In the preferred arrangements taught in this application, restraining straps which are shorter and stronger than the leads constrain the motion of the elements as they move away from one another to deform the leads. The preferred aspects of copending, commonly assigned U.S. patent application Ser. No. 08/532,528, issued or to be issued as U.S. Pat. No. 5,798,286, disclose further improvements in the basic process taught in the '964 patent, with respect to the processing of arrays of individual semiconductor chips bonded to leads on a single dielectric element so that the leads associated with all of the separate chips can be deformed and in a single operation.
The disclosures of all of the aforementioned patents and applications are incorporated herein by reference.
Despite these advances in the art of making microelectronic assemblies, still further improvements would be desirable.
SUMMARY OF THE INVENTION
One aspect of the present invention provides methods of making microelectronic assemblies. A method in accordance with this aspect of the invention includes the step of providing a sheet including a main portion and a plurality of gaps extending through the sheet. These gaps partially surround and define a set of elongated lead regions in the sheet. Each lead region has a fixed end connected to the main portion of the sheet and a tip end remote from the fixed end. The lead regions of the sheet include conductors extending between the tip ends and the fixed ends. In a further step of the method, the sheet is juxtaposed with a microelectronic component so that the tip ends of the lead regions on the sheet are aligned with contacts on the microelectronic element. The tip ends of the
Fjelstad Joseph
Smith John W.
Chambliss Alonzo
Chaudhuri Olik
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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