Method of fabricating a memory transistor array utilizing...

Details Method of fabricating a memory transistor array utilizing... Method of fabricating a memory transistor array utilizing...

2006-05-23

2006-05-23

Chambliss, Alonzo (Department: 2814)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C438S261000, C438S591000, C438S622000, C438S666000, C257S690000, C257S692000, C257S696000, C257S700000, C257S758000, C257S773000

Reexamination Certificate

active

07049180

ABSTRACT:
A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

REFERENCES:
patent: 5306941 (1994-04-01), Yoshida
patent: 5877537 (1999-03-01), Aoki
patent: 6381166 (2002-04-01), Yoshida et al.
patent: 6765271 (2004-07-01), Iijima
patent: 6891262 (2005-05-01), Nomoto et al.
patent: 2001/0052958 (2001-12-01), Ogawa

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