Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2000-05-12
2002-04-23
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S237000, C438S599000
Reexamination Certificate
active
06376284
ABSTRACT:
BACKGROUND OF THE INVENTION
Diode arrays are well known memory storage arrays used in semiconductor memory devices. A selected diode is typically addressed via digit line and word line selection. A resistance of a programmable resistor in series with the selected diode is controlled to select a desired memory state. In one case the programmable resistor may be an ovonic element, such as a chalcogenide material. The internal structure of the chalcogenide is modified to alter its resistance and therefore its “logic” state. The modification of the structure is ovonic and is dependent on the current which is applied to the element through the diode. It is desirable to reduce stray resistance which may be in series with the diode, since by reducing the stray resistance the ovonics can be more closely controlled with less current, thereby reducing power requirements.
SUMMARY OF THE INVENTION
The invention includes a method for forming a semiconductor device wherein a conductive element within the substrate is strapped by another conductive layer above. In one currently envisioned embodiment, another conductive layer will be interposed between the substrate and the strapping layer. In one exemplary preferred implementation, the semiconductor device will be a memory device comprising a diode serially connected to a programmable resistor. The diode is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal structure wherein the strapping layer is a second metal layer overlying metal wordlines.
In a method of a first embodiment, the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material. Typically a layer of titanium silicide is formed on the buried digit line.
In an exemplary method of forming a second embodiment in accordance with the present invention, diodes are formed, each having a maximum width equal to f, which may be equal to the minimum photolithographic limit of the photolithographic equipment being used, and distanced one from the other along a length of the digit line by a maximum distance equal to f; at least portions of the diodes are masked; at least a portion of an insulative material interposed between two diodes is removed to expose the buried digit line; and the conductive plug is formed in contact with the exposed portion of the buried digit line. After the formation of a programmable resistor in series with the diode a wordline is formed in electrical communication with each of the programmable resistors, and an insulative layer is formed overlying each wordline. Next an insulative spacer layer is deposited and etched to expose the conductive plug. The strapping layer is then formed overlying and in contact with the conductive plug.
In the second embodiment the width of the diode is equal to f and the electrically conductive plug is formed within a distance f from a sidewall of the diode. An electrically insulative spacer is interposed between the plug and the sidewall of the diode. In this embodiment the diode and the plug are made of polycrystalline silicon, although it is possible to use any conceivable diode structure, for example a metal/semiconductor. In the second embodiment the cathode of the diode is fabricated in the substrate and the anode is fabricated overlying the substrate or vice versa.
In the typical memory array of the invention the programmable resistor is ovonic and the array is a mesa type structure. The diodes are either planar or container structures.
The invention provides redundancy since the digit line is a buried component and the strapping layer is an upper component. Thus, even if the metal of the strapping layer breaks, operation of the memory device is maintained through the buried digit line. Thus the device has better electromigration reliability, and there is no memory disturbance from cell to cell due to the collection of current in the digit line.
There is space savings when using the structure of the second embodiment, since the area between cells is no longer just isolation space but is used instead for contact to the buried digit line, thereby providing efficient spacing of the cell for high compaction while at the same time. providing good cell to cell isolation.
By using the double metal scheme of the invention the series resistance to the diode is reduced to the diode/prograiiuiable resistor structure. This resistance is decreased even further by providing a strapped conductive plug for every two diodes of the array and physically interposed therebetween. By using Titanium silicide on the buried digit line in conjunction with the strapped metal layer the best packing density is achieved with minimal processing steps. In addition the titanium silicide is used to minimize the number of connections needed to connect the strapping material and buried digit line.
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Gonzalez Fernando
Sandhu Gurtej S.
Violette Mike P.
Fletcher Yoder & Van Someren
Fourson George
Micro)n Technology, Inc.
Pham Thanh V
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