Method of fabricating a memory cell array area and a peripheral

Details Method of fabricating a memory cell array area and a peripheral Method of fabricating a memory cell array area and a peripheral

1995-06-07

1998-07-14

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 48, H01L 218239

Patent

active

057803102

ABSTRACT:
The invention provides a semiconductor substrate structure for semiconductor integrated circuit devices including a memory cell array area involving both stacked capacitors and transistors and a peripheral circuit area involving transistors. A portion of the device in the memory cell area has a larger thickness than that of the peripheral circuit area. The transistors involved in the memory cell array area possess different properties from that of the transistors involved in the peripheral circuit area. The substrate structure has a surface region comprising a first impurity concentration region underlying a recessed portion in the memory cell array area and an opposite region having a second impurity concentration from that of the high impurity concentration region so that a surface in the memory cell area exists at a lower level than that of a surface in the peripheral area. The recessed portion makes difference in surface levels of the device reduced, resulting in fine patterns of photo-lithography promoting high integration. Both the first and second impurity concentrations are so determined as to allow the transistors involved in the both areas to exhibit best performances and an excellent properties respectively.

REFERENCES:
patent: 4554729 (1985-11-01), Tamimura et al.
patent: 4882289 (1989-11-01), Moriuchi et al.

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