Method of fabricating a layered electronic assembly having compe

Details Method of fabricating a layered electronic assembly having compe Method of fabricating a layered electronic assembly having compe

1989-08-16

1990-12-25

Ball, Michael W.

Adhesive bonding and miscellaneous chemical manufacture

Methods

Surface bonding and/or assembly therefor

29830, 29834, 156295, 156321, 156378, 156379, 156556, 357 75, B32B 3120

Patent

active

049800027

ABSTRACT:
Layered electronic assemblies are fabricated from a plurality of integrated circuit chips that have respective thicknesses which vary from chip to chip, and have I/O leads which are offset from one edge of the chip on which they lie by respective distancess which vary from chip to chip. Each layered electronic assembly is formed by the steps of: (a) disposing an uncured adhesive material between one of the chips "i" and another of the chips i+1 without regard to their respective thicknesses and respective distances by which their I/O leads are offset; (b) moving the chips i and i+1 relative to one another with the uncured adhesive material lying between them until their I/O leads are aligned and separated by a predetermined spacing; (c) curing the adhesive between the chips i and i+1 while their I/O leads are kept aligned and separated at the predetermined spacing; and, (d) repeating in a serial fashion, the forming, moving, and curing steps once for each remaining chip in said plurality, where i equals 1, 2, . . . N. Using this process, 100% of the electrically functional chips which are cut from a semiconductor wafer can be used without sacrificing any accuracy with which the I/O leads are aligned on the stack face.

REFERENCES:
patent: 3834966 (1974-09-01), Kelly
patent: 4398660 (1983-08-01), Pampalone et al.
patent: 4704319 (1987-11-01), Belanger et al.
patent: 4706166 (1987-11-01), Go
patent: 4777374 (1988-10-01), Nakata et al.

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