Fishing – trapping – and vermin destroying
Patent
1987-04-09
1988-03-08
Hearn, Brian E.
Fishing, trapping, and vermin destroying
357 22, 156656, 156653, 148DIG88, 437184, 437944, 437911, H01L 21265
Patent
active
047299673
ABSTRACT:
Method of fabricating a junction field effect transistor, specifically a static induction transistor, which may be of GaAs. Elongated N-type source regions are formed in an N-type epitaxial layer of semiconductor material grown on a substrate. A tri-level mask is formed having elongated openings exposing portions of the epitaxial layer intermediate between the source regions. The openings are wider at the bottom than at the top. P-type gate regions are formed by ion-implanting P-type doping material through the mask openings. Silicon dioxide is deposited through the openings by angle evaporation to form generally trapezoidal-shaped temporary gate members over the gate regions. The tri-level mask is removed, a layer of silicon nitride is deposited, and a layer of masking material is deposited. Some of the masking material is removed; then the temporary gate members and silicon nitride immediately adjacent thereto are removed. Metal for making ohmic contact to the P-type gate regions is deposited through the resulting openings. The remaining masking material is removed, openings are formed in the silicon nitride over the N-type source regions, and metal for making ohmic contact to the N-type source regions is deposited in the openings.
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Bencuya et al., "Static Induction Transistors Optimized for High Voltage Operation and High Microwave Power Output", IEEE Trans. on Electron Devices, vol. ED-32, No. 7, Jul. 1985, pp. 1321-1327.
GTE Laboratories Incorporated
Hearn Brian E.
Keay David M.
Wilczewski Mary A.
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