Method of fabricating a high voltage semiconductor device...

Details Method of fabricating a high voltage semiconductor device... Method of fabricating a high voltage semiconductor device...

2002-05-08

2003-12-09

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making regenerative-type switching device

C438S140000, C438S694000, C438S723000, C438S764000

Reexamination Certificate

active

06660570

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a high voltage semiconductor device using semi-insulating polycrystalline silicon (SIPOS) and a method for fabricating the same.
2. Description of the Related Art
As application equipment becomes larger in size and capacity, high voltage semiconductor devices having a high breakdown voltage, a high current and a fast switching speed become more important. In order to decrease power loss in a conductive state even while a large amount of current is flowing, the saturation voltage of high voltage semiconductor devices is required to be low. High voltage semiconductor devices are fundamentally required to have a characteristic of resisting a reverse high voltage applied to both ends thereof in an off-state or at the moment the device is turned off. That is, high voltage semiconductor devices are fundamentally required to have a high breakdown voltage. A variety of breakdown voltages of power semiconductor devices are required to be in a range from several tens of volts to several thousands of volts.
Generally, the breakdown voltage of a semiconductor device largely depends on a depletion region extending from a PN junction, and particularly, is greatly influenced by the curvature of the depletion region. In particular, for a planar junction, an electric field is concentrated on the edges, which have a large curvature, thereby decreasing the overall breakdown voltage. Accordingly, a number of methods have been proposed in order to obtain high breakdown voltage by preventing an electric field from being concentrated on the edge of a junction. Some of these methods include a method using a field plate, a method using a field limit ring, and a method using both of these methods. In addition, a method of forming a semi-insulating polycrystalline silicon layer on a semiconductor substrate having a planar junction has been researched and developed.
FIG. 1
is a sectional view illustrating an example of a conventional high voltage semiconductor device. Referring to
FIG. 1
, a semiconductor substrate
10
doped with first conductivity type impurities such as N-type impurities is used as a collector region. A base region
11
doped with second conductivity type impurities such as P-type impurities is formed in part of the semiconductor substrate
10
. An N-type emitter region
12
is formed in a predetermined upper portion of the base region
11
. A field limit ring
13
is disposed so that it is separated from the edge of the base region
11
by a predetermined distance in the semiconductor substrate
10
. A channel stopper
14
doped with N-type impurities is formed in a field region separated from the field limit ring
13
. The field limit ring
13
restrains an electric field from concentrating on the edge of a PN junction formed by the semiconductor substrate
10
and the base region
11
. A semi-insulating polycrystalline silicon layer
15
and an oxide layer
16
deposited by chemical vapor deposition (CVD) are formed on the semiconductor substrate
10
. The oxide layer
16
serves as a protective layer and may be substituted by a nitride layer. An emitter electrode
17
, a base electrode
18
, an equipotential electrode
19
and a collector electrode
20
are formed to be electrically connected to the emitter region
12
, the base region
11
, the channel stopper
14
and the semiconductor substrate
10
, respectively.
High voltage semiconductor devices having such a structure have many advantages such as realization of high breakdown voltage and reduction of the area of a field region. However, the semi-insulating polycrystalline silicon layer
15
directly contacts the surface of the semiconductor substrate
10
, thus increasing leakage current. In addition, the semi-insulating polycrystalline silicon layer
15
existing on the semiconductor substrate
10
between the base region
11
and the emitter region
12
in an active region decreases a direct current (DC) gain h
FE
in a low collector current range, thereby deteriorating the electrical characteristics of devices. Moreover, since the oxide (or nitride) layer
16
is formed by CVD as a protective layer, the interface between the semiconductor substrate
10
and the semi-insulating polycrystalline silicon layer
15
and the interface between the semi-insulating polycrystalline silicon layer
15
and the CVD oxide (or nitride) layer
16
are unstable. This may frequently cause dielectric breakdown.
FIG. 2
is a sectional view illustrating another example of a conventional high voltage semiconductor device. The high voltage semiconductor device of
FIG. 2
has a smaller leakage current than the high voltage semiconductor device of FIG.
1
. In
FIGS. 1 and 2
, the same reference numerals denote the same region or member, and thus descriptions of the regions that are the same will be omitted.
Referring to
FIG. 2
, an oxide layer
21
, a first semi-insulating polycrystalline silicon layer
22
and a second semi-insulating polycrystalline silicon layer
23
are sequentially deposited on the surface of a semiconductor substrate
10
serving as a collector region and having a base region
11
, an emitter region
12
and a channel stopper
14
. The oxide layer
21
restrains leakage current flowing between the first semi-insulating polycrystalline silicon layer
22
and the semiconductor substrate
10
, that is, the oxide layer
21
restrains leakage current flowing over the surface of the semiconductor substrate
10
. The first semi-insulating polycrystalline silicon layer
22
has an oxygen concentration of about 9%, and the second semi-insulating polycrystalline silicon layer
23
has an oxygen concentration of about 20-50%. Accordingly, the semi-insulating polycrystalline silicon layer
23
serves as a protective layer like a CVD oxide layer and shows a good interface state with the first semi-insulating polycrystalline silicon layer
22
so that dielectric breakdown can be restrained. A base electrode
18
connected to the base region
11
through a contact is formed on the second semi-insulating polycrystalline silicon layer
23
so that it extends to a field region. Accordingly, the base electrode
18
also serves as a metal field plate.
However, in a high voltage semiconductor device having such a structure, the semi-insulating polycrystalline silicon layers
22
and
23
existing on the semiconductor substrate
10
between the base region
11
and the emitter region
12
in an active region still decrease DC gain h
FE
in a low collector current range, thereby deteriorating the electrical characteristics of the device. In addition, it is difficult to understand the stacked state of the first and second semi-insulating polycrystalline silicon layers during the progress of fabrication. Moreover, it takes much time to deposit the second semi-insulating polycrystalline silicon layer
23
having a high oxygen concentration, and dry etching requiring a large amount of time and cost should be performed to pattern the second semi-insulating polycrystalline silicon layer
23
.
SUMMARY OF THE INVENTION
To solve the above problems, it is a first object of the present invention to provide a high voltage semiconductor device having improved electrical characteristics and high breakdown voltage, using a semi-insulating polycrystalline silicon layer.
It is a second object of the present invention to provide a method for fabricating the high voltage semiconductor device at a low cost and in a short fabrication time.
Accordingly, to achieve the first object of the invention, there is provided a high voltage semiconductor device includes a semiconductor substrate of a first conductivity type used as a collector region, the semiconductor substrate having an active region and a field region; a base region of a second conductivity type formed in the active region of the semiconductor substrate; an emitter region of a first conductivity type formed in the base region; a

Affiliated with

Also associated with

Rating

Method of fabricating a high voltage semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating a high voltage semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a high voltage semiconductor device... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3122640