Method of fabricating a high resistance polysilicon load resisto

Fishing – trapping – and vermin destroying

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437 47, 437918, 148DIG136, H01L 2170

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051680769

ABSTRACT:
A load resistor for use in a semiconductor integrated circuit consists of two portions of conductive material, typically strips of either a silicide or a composite polycrystalline silicon layer and silicide layer formed thereon, formed on a semiconductor substrate and separated from each other by a selected distance. An electrically conductive dopant diffusion barrier is formed on the first and second portions of conductive material. A polycrystalline silicon material is then placed on the structure such that one portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the first portion of conductive material and the other portion of the polycrystalline silicon material is in ohmic contact through the diffusion barrier with the second portion of conductive material. Typically the polycrystalline silicon material is placed on an insulation layer formed on the semiconductor substrate in the portion of the substrate between the two portions of conductive material. The diffusion barrier prevents any dopant from the conductive material from diffusing into the polycrystalline silicon material thereby allowing the polycrystalline silicon material to function as a load resistor having a high resistance in the giga-ohms range. Subsequent high temperature processing of the structure does not change the resistance of the polycrystalline silicon because the dopant diffusion barrier prevents any dopant from the underlying conductive material from diffusing into the polycrystalline silicon material.

REFERENCES:
patent: 4329706 (1982-05-01), Crowder
patent: 4774203 (1988-09-01), Ikeda et al.
patent: 4835118 (1989-05-01), Jones, Sr. et al.
patent: 4903096 (1990-02-01), Masuoka et al.
patent: 4931411 (1990-06-01), Tigelaar et al.
patent: 5013678 (1991-05-01), Winnerl et al.
patent: 5013686 (1991-05-01), Choi et al.
patent: 5037766 (1991-08-01), Wang
IEEE VLSI Multilevel Interconnection Conference, Jun. 1986, pp. 530-536; N. McIntyre et al. entitled "Self Aligned Silicide Interconnection . . . ".
Journal of Vacuum Science and Technology: Part A, No. 4, 1987, pp. 2184-2189; E. O. Ristolainen et al. entitled "A Study of Nitrogen-Rich . . . ".
IEEE Transactions on Electron Devices, vol. 36, No. 9, Sep. 1989, pp. 1657-1662; M. Minami et al. entitled "A New Soft-Error-Immune Static . . . ".
IEEE Transactions on Electron Devices, vol. 35, No. 3, Mar. 1988, pp. 298-301; R. Saito et al. entitled "A Novel Scaled-Down Oxygen-Implanted . . . ".

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