Method of fabricating a high performance bipolar and MOS device

Details Method of fabricating a high performance bipolar and MOS device Method of fabricating a high performance bipolar and MOS device

1989-03-06

1990-05-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437 57, 437162, 437200, 357 43, H01L 2128, H01L 2122

Patent

active

049277758

ABSTRACT:
An improved method of fabricating a high performance bipolar and MOS integrated circuit is provided. The method utilizes a single polysilicon layer, a self-aligned emitter-base structure, self-aligned silicide contacts, and silicon dioxide sidewall spacers to obtain reduced emitter and base resistance, reduced collector to base capacitance, greater switching speed, and a higher packing density. The method also has the advantage of being simple and compatible with a method of fabricating MOS devices which improves performance and yield.

REFERENCES:
patent: 4438556 (1984-03-01), Komatsu et al.
patent: 4764480 (1988-08-01), Vora
"Is BiCMos the Next Technology Driver?" by Bernard C. Cole, Electronics, Feb/1988, pp. 55-57.
"Self-Aligned Transistors with Polysilicon Emitters for Bipolar VLSI" by Cuthbertson et al., IEEE Electron Devices, vol. ED-32, No. 2, Feb. 1985, pp. 242-247.

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