Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2002-01-24
2003-07-22
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S785000
Reexamination Certificate
active
06596602
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, especially a method for forming a capacitor structure in the semiconductor device.
DESCRIPTION OF THE PRIOR ART
Among various types of semiconductor device, dynamic RAMs (DRAMs) have been well known in the art as memory devices where the input and output of information can be performed as needed. A typical memory cell of such a DRAM is structurally simple and comprises two components: a transfer transistor and a capacitor. Therefore, it is applied very extensively in various fields because of such a simple circuitry most suitable for providing a highly integrated semiconductor device.
Also, in the latest technology of semiconductor device, system LSIs are becoming important. For providing such semiconductor devices, various mixed semiconductor devices with fundamentally different types of components have been developed and studied, such as a logic-mixed memory device in which a logic circuit and a memory circuit are mounted together on a single semiconductor chip and an analog-mixed logic device in which a logic circuit and an analog circuit are mounted on a single semiconductor chip Just as in the case with the DRAM mentioned above, the mixed semiconductor device has a memory cell consisting of a transfer transistor and a capacitor.
In conjunction with the further increase in integration of semiconductor device, a capacitor having a three-dimensional structure has been developed and used for that memory cell. The reason of fabricating the three-dimensionally structured capacitor is the follow. That is, in connection with the fabrication of finer and denser semiconductor device, the reduction in the occupied area of a capacitor becomes indispensable. In this case, however, the capacity of the capacitor should be kept at more than the predetermined level for ensuring the reliable and stable operation of a memory part of the semiconductor device. Therefore, it becomes indispensable to change the shape of each electrode in the capacitor from a flat shape into a three-dimensional shape so as to expand the surface area of the electrode in its reduced area occupied in the capacitor.
For such a three-dimensional structure of the capacitor in the memory cell, there are two structural designs (i.e., a stack structure and a trench structure). Each of these structures has its own merits and demerits. The stack structure has considerable tolerance to an incident alpha-ray or a noise from any circuit or the like, allowing the operation of the capacitor in stable even at a comparatively small capacitance value. Therefore, such a stack structure may be effective in the process of fabricating a semiconductor device even though the chip employs design rules of approximately 0.10 &mgr;m.
Recently, furthermore, the capacitor having the stack structure (hereinafter, such a capacitor is referred to as a stacked-type capacitor) requires a dielectric film (i.e., a capacity insulator film) with an extremely high dielectric constant for ensuring a predetermined capacitance value in a very small area. Therefore, several materials have been intensively studied for the dielectric film. The materials include insulating materials such as tantalum pentoxide (Ta
2
O
5
), SrTiO
3
(hereinafter, simply referred to as a STO), a (Ba, Sr)TiO
3
(hereinafter, simply referred to as a BST), and Pb(Zr, Ti)O
3
(hereinafter, simply referred to as a PZT). Moreover, it becomes necessary to provide a new conductive material to be provided as a lower electrode of the above stacked-type capacitor for the purpose of ensuring a high reliability of the capacitor by means of an appropriate combination of the above high dielectric insulator material with the lower electrode. In the Digest of Technical Papers, pp. 831-834, of the annual IEEE International Electron Devices Meeting (IEDM) held on 1994, a STO film is used as a capacity insulator film and ruthenium dioxide (RuO
2
) is used as a conductive material of a lower electrode. In addition, the same kind of the capacitor structure can be found in Japanese Patent Application Laying-open No. 2000-114482.
Referring now to FIG.
11
A and
FIG. 11B
, we will describe the configuration of the stacked-type capacitor having the conventional high dielectric constant film. In
FIG. 11A
, there is shown a schematic plan view of the stacked-type capacitor only with a lower electrode
105
, a capacity insulator film
106
, and an upper electrode
107
for simplified illustration.
FIG. 11B
is a cross sectional view of the stacked-type capacitor along the break line X-Y in FIG.
11
A.
As shown in
FIG. 11B
, a diffusion layer
102
with a N-type electric conduction is formed on a predetermined area of the surface of a silicon substrate
101
with a P-type electric conduction. A part of an insulator film
103
on the silicon substrate
101
is opened and filled with a plug
104
. Also, the lower electrode
105
is formed on the insulator film
103
so as to directly cover the insulator film
103
. Thus, the lower electrode
105
can be electrically connected to the diffusion layer
102
through the plug
104
.
As shown in FIG.
11
A and
FIG. 11B
, furthermore, the capacity insulator film
106
is formed on the side and top of the lower electrode
105
and the exposed surface of the interlayer insulator film
103
. Here, the interlayer insulator film
103
is made of a metal film such as a ruthenium oxide film, while the capacity insulator film
106
is made of another metal film such as a Ta
2
O
5
film or a STO film. Then, an upper electrode
107
is formed so as to cover the whole substrate. Here, the upper electrode
107
may be made of the same material as that of the lower electrode
105
.
The present inventors have been thoroughly studied about the capacitor having a Metal/Insulator/Metal (MIM) structure in which a high dielectric constant material such as one described above is used as a capacity insulator film. Consequently, they found the fact that a leak current in the capacity insulator film increased as the measuring temperature increased when the capacity insulator film was made of a metal oxide film such as a tantalum pentoxide (Ta
2
O
5
), zirconium dioxide (ZrO
2
), hafnium dioxide (HfO
2
), STO (SrTiO
3
), BST ((Ba,Sr) TiO
3
), or PZT (Pb(Zr,Ti) O
3
) film.
In the following description, we will give a brief explanation of the dependence of the above leak current on measuring temperature with reference to FIG.
12
. In this figure, there is shown one of the features of a capacitor having the above MIM structure (hereinafter, simply referred to as a MIM capacitor) in which a STO film is used as its capacity insulator film. In this case, furthermore, the applied voltage between the lower electrode and the upper electrode is in the range of −1 volt to +1 volt.
In the graph shown in
FIG. 12
, the horizontal axis represents the inverse (1/T) of an absolute temperature (i.e., a measuring temperature measured in kelvins (K)), while the vertical axis represents the logarithm of leak current (J/T
2
) in the capacity (insulator) film. As shown in
FIG. 12
, the leak current (J/T
2
) in the capacitor is substantially in inverse proportion to the inverse (1/T) of the measuring temperature. In other words, the leak (J/T
2
) in the capacitor can be restricted with the thermal release of electrons from the lower or upper electrode (i.e., the capacitor electrode) to the capacitive insulator film. In the prior art, therefore, the leak current (J/T
2
) in the capacity film dramatically increases as the measuring temperature increases. By the way, it is also known that the dependence of such a leak current on temperature is varied with respect to the above applied voltage. Whatever the case may be, however, the leak current is proportional to the measuring temperature.
For operating the semiconductor device, a guaranteed operating temperature of the semiconductor device should be of about 150° C. at maximum. Notably in the case of the logic mixed
Iizuka Toshihiro
Yamamoto Tomoe
Elms Richard
NEC Corporation
Owens Beth E.
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