Method of fabricating a high density masked programmable read-on

Details Method of fabricating a high density masked programmable read-on Method of fabricating a high density masked programmable read-on

1987-04-27

1989-01-03

Carroll, J.

357 15, 357 40, 357 47, 357 59, H01L 2702, H01L 2948, H01L 2904

Patent

active

047960744

ABSTRACT:
The word line pitch within a read-only memory is decreased, thereby increasing the cell density within the memory, without imposing any additional or stricter spacing rules or fabrication techniques utilized in the manufacture of the read-only memory integrated circuit chip. The read-only memory is comprised of a plurality of memory cells. A two-dimensional semiconductor diode layer is laid down on a plurality of word lines which have previously been disposed upon a semiconductor supporting substrate. The semiconductor diode layer is disposed on the plurality of word lines without regard to any alignment criteria. A programmable material is inlaid on the Schottky diodes and a plurality of bit lines laid upon the programmable material. The bit lines and word lines are orthogonally disposed with respect to the Schottky diodes so that each diode is uniquely addressed by one word line and one bit line. The programmable material may be laid upon the Schottky diode as a two-dimensional layer or as a plurality of strips or paths without regard to any alignment criteria. Because a single alignment is required in each of two orthogonal dimensions between the word line and the Schottky diode in one dimension, or the bit line and Schottky diode in another dimension, the center-to-center word line or bit line pitch is reduced to four microns and utilizing a fabrication methodology based a two-micron rule.

REFERENCES:
patent: 4442507 (1984-04-01), Roesner
patent: 4569120 (1986-02-01), Stacy et al.
patent: 4569121 (1986-02-01), Lim et al.
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4692787 (1987-09-01), Possley et al.

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