Method of fabricating a heterojunction bipolar transistor

Details Method of fabricating a heterojunction bipolar transistor Method of fabricating a heterojunction bipolar transistor

1991-07-02

1994-02-08

Kunemund, Robert

Fishing, trapping, and vermin destroying

437 81, 437105, 437107, 437126, 437133, H01L 21265

Patent

active

052847837

ABSTRACT:
A method of fabricating a semiconductor device having an epitaxial layer of a group III-V semiconductor material provided on an underlying crystal layer with a lattice matching therewith, the semiconductor material being doped to the p-type by addition of beryllium and selected from a group including gallium aluminum arsenide and indium gallium aluminum arsenide, in which the method comprises steps of growing the epitaxial layer on the underlying crystal layer, adding beryllium to a concentration level of about 5.times.10.sup.19 atoms/cm.sup.3 to about 5.times.10.sup.20 atoms/cm.sup.3 to the semiconductor material, and adding indium by an amount of about 0.5 mole percent to about 8 mole percent with respect to group III elements in the semiconductor material.

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