Method of fabricating a gate array integrated circuit including

Details Method of fabricating a gate array integrated circuit including Method of fabricating a gate array integrated circuit including

1995-06-07

1998-02-24

Niebling, John

Fishing, trapping, and vermin destroying

437 8, 437 50, H01L 2170

Patent

active

057211515

ABSTRACT:
A plurality of macro-arrays are formed on a semiconductor substrate. Each macro-array includes a logic area in which a plurality of interconnectable logic gates are formed, and an Input/Output (I/O) area in which a plurality of I/O devices are formed. I/O terminals are formed outside the I/O area, which enable the logic devices of the macro-arrays to be interconnected with the logic devices of the other macro-arrays via the I/O devices. Alternatively, connections can be made directly to the logic devices. The interconnections are made using a pattern of conductors such that the macro-arrays are linked to form a composite gate array which provides a programmed logical functionality. A number of contiguous macro-arrays which provide the required number of gates are used, with the unused macro-arrays being cut away and discarded. The array is mounted on and electrically interconnected with a printed circuit board or other support member using a flip-chip arrangement which provides access to internal I/O connections.

REFERENCES:
patent: 4733288 (1988-03-01), Sato

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