Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-06-24
2000-03-07
Mai, Son
Static information storage and retrieval
Floating gate
Particular biasing
36518529, 257316, 257326, G11C 1604
Patent
active
060348968
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates in general to Electrically Erasable and Programmable Read-Only Memory (E.sup.2 PROM), and more particularly to a method of fabricating a flash E.sup.2 PROM with fast programming speed and low operating voltages.
BACKGROUND OF THE INVENTION
Flash memory is a modified form of E.sup.2 PROM which can be erased one block at a time and can be programmed one bit at a time. At the time of filing this application, flash memory chips are available in densities of up to 32M bits. Large data storage capacity with complete nonvolatility, results in numerous applications for such chips, ranging from cellular telephones, solid-state disks and memory cards. Such applications have traditionally been the domain of ROM, conventional E.sup.2 PROM, battery-backed RAM, static RAM (SRAM) and magnetic storage.
A flash E.sup.2 PROM cell resembles an ordinary MOS (Metal-Oxide-Semiconductor) transistor, except for the addition of a floating gate, which is buried in the insulator between the substrate and the conventional control gate. Charge stored on the floating gate alters the threshold voltage (V.sub.th) of the device as measured at the control gate. Since the floating gate and the control gate are both stacked directly above the transistor channel, very high densities can be achieved. Even higher densities can be obtained by self aligning the control and floating gates to the source and drain regions.
The cell is programmed and erased by adding electrons to and removing electrons from the floating gate, respectively. A cell with a high threshold voltage (V.sub.th) is in its "0" state. After erasure has been completed, the threshold voltage is reduced resulting in a "1" state. The conductivity of the channel determines the information stored in the memory cell (i.e. current flowing through the channel is detected by sense-amplifier circuitry as a "1", while the absence of current is detected as a "0").
Flash E.sup.2 PROM technology has received industry-wide attention recently. Due to its simple single transistor cell architecture, flash memory may eventually cost less to make than DRAM (Dynamic Random Access Memory).
The channel hot electron programming method, used in conventional flash E.sup.2 PROM cells, requires biasing the device at high drain voltage (6 to 8 V) to generate hot electrons. This results in additional circuit complexity and cost (ie. an additional external voltage supply), which is a particular disadvantage in mobile applications such as cellular telephones, etc.
Furthermore, the channel hot electron injection method used for programming conventional flash E.sup.2 PROM cells, generates very high lateral source-to-drain currents (in the range of milliamperes). These high currents limit the number of cells that can be programmed at one time.
Existing flash E.sup.2 PROM cells also suffer from slow programming speed (.about.10 .mu.s) which prevents their widespread application as a replacement for RAMs and electronic hard disks. If the device gate length is scaled down in order to reduce the programming time, then punchthrough between the source and drain is likely to occur.
DISCUSSION OF PRIOR ART
A well known early prior art predecessor to modern day flash memory devices is the FAMOS (floating-gate avalanche-injection MOS) memory. This device is described in a number of publications, including: Dov Frohman-Bentchowsky, "A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory"; IEEE Journal of Solid State Circuits, Vol. SC-6, No. 5, October 1971, pp 301-306; Ron D. Katznelson and Dov Frohman-Bentchowsky, "An Erase Model for FAMOS EPROM Devices"; IEEE Transactions on Electron Devices, Vol. ED-27, No. 9, September 1980, pp 1744-1752; and U.S. Pat. No. 4,203,158 (Frohman-Bentchkowsky, et al).
Another prior art flash memory device is described in Masatada Horiuchi and Hisao Katto, "FCAT-A Low-Voltage High Speed Alternative n-Channel Nonvolatile Memory Device"; Transactions on Electron Devices, Vol. ED-26, No. 6, June 1979, pp. 914-918. The
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"A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory", IEEE J. Solid-State Circuits, vol. SC-6, No. 5, pp. 301-306, Oct. 1971.
"An Erase Model for FAMOS EPROM Devices", IEEE Trans. Electron Devices, vol. ED-27, No. 9, pp. 1744-1752, Sep. 1980.
Gulersen Elvira
Kalastirsky Ivan
Ng Wai Tung
Ranaweera Jeewika Chandanie
Salama Clement Andre T.
Mai Son
The University of Toronto Innovations Foundation
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