Method of fabricating a dynamic random access memory stacked cap

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

055433464

ABSTRACT:
A DRAM capacitor and a method for fabricating the same, capable of achieving an increase in surface area and thereby an increase in capacitance while reducing the topology, by simply forming a conduction layer, as a charge storage electrode, comprised of conduction spacers around a double-layer pin-shaped conduction layer pattern or a combination of a central conduction layer pattern and an outer conduction layer pattern having an upwardly-opened dome structure surrounding the central conduction layer pattern, using an etch rate difference between insulating films.

REFERENCES:
patent: 5126280 (1992-06-01), Chan et al.
patent: 5137842 (1992-08-01), Chan et al.
patent: 5403766 (1995-04-01), Miyake
patent: 5432116 (1995-07-01), Keum et al.
patent: 5468670 (1995-11-01), Ryou

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