Method of fabricating a charge transfer channel covered by a ste

Details Method of fabricating a charge transfer channel covered by a ste Method of fabricating a charge transfer channel covered by a ste

1980-01-18

1982-02-02

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29579, 148 15, 148187, 357 24, 357 41, 357 91, 365149, H01L 21223, H01L 2126

Patent

active

043132537

ABSTRACT:
The disclosed memory cell is comprised of a charge storage region and an adjacent charge transfer channel. A deep dopant layer extends throughout the charge storage region, and a shallow dopant layer extends throughout the charge storage region plus part-way through the charge transfer channel. Overlying the charge storage region is a first conductor that is completely covered by a thick insulating layer. This thick insulating layer also extends into the charge transfer channel part-way over the shallow dopant layer. A thin insulating layer covers the remaining portion of the channel. Lying on this thin insulating layer and extending onto the thick insulating layer is a second conductor. Parasitic capacitance and catastrophic shorts between the two conductors are minimized by the thick insulating layer; charge storage capacity of the storage region is maximized by the two dopant layers lying therein; and cell length is minimized by the thick insulating layer and underlying shallow dopant layer in the charge transfer channel.

REFERENCES:
patent: 4112575 (1978-09-01), Fu et al.
patent: 4125933 (1978-11-01), Baldwin et al.
patent: 4145803 (1979-03-01), Tasch
patent: 4164751 (1979-08-01), Tasch
patent: 4240195 (1980-12-01), Clemens et al.
patent: 4240845 (1980-12-01), Esch et al.
patent: 4251571 (1981-02-01), Garbarino et al.

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