Method of Fabricating a capacitor structure having...

Details Method of Fabricating a capacitor structure having... Method of Fabricating a capacitor structure having...

2003-01-29

2004-12-07

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S246000, C438S389000, C438S255000, C438S659000

Reexamination Certificate

active

06828207

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory and a method of fabricating the same, and more particularly, to a capacitor of a semiconductor memory device having a hemispherical grained (HSG) layer and a method of fabricating the same.
2. Description of Related Art
A conventional forming method of a semiconductor memory device is explained in the following manner. A trench is formed in a silicon substrate
1
and this trench is filled with a CVD oxide. The trench is planarized by chemical mechanical polishing (CMP) technique, so that a trench isolation region
2
is formed (see FIG.
1
A).
Thereafter, a layer of thin oxide
3
is grown on all the surfaces by thermal oxidation. Layers of polycrystalline silicon
4
and tungsten
5
are next deposited by CVD, and etched in order to define gate electrodes
6
of MOS transistors and interconnects
7
(see FIG.
1
B).
Next, a layer of interoxide
8
is deposited by CVD, and etched to define a bitline contact hole
9
in the layer of interoxide
8
. Layers of polysilicon
10
and tungsten suicide
11
are deposited on all the surfaces, and etched to form a bitline
12
(see
FIG. 1C
)
Moreover, layers of interoxide
13
silicon nitride
14
are respectively deposited by CVD. Cell contact holes
15
are defined both in layers interoxide
13
and silicon nitride
14
by etching. A layer of polycrystalline silicon
16
heavily doped impurities is deposited on all the surfaces, and is polished by CMP method. Only the contact holes
15
are filled with the polycrystalline silicon
16
(see FIG.
2
A).
A layer of a thick insulator
17
is deposited by CVD, and holes are opened in the insulator
17
by etching to form lower electrodes. A layer of a amorphous silicon
18
, which is doped phosphorous of 0.5E20 to 3E20 cm-3, is deposited by CVD, and only the opening holes are filled with resists
19
(see FIG.
2
B).
Next, after all the surfaces are etched, the insulators
17
are removed by hydrogen fluoride solution, resulting that cylindrical lower electrodes
20
are formed (see FIG.
2
C).
Heat treatment is carried out in a silane gas ambient under low pressure, and hemispherical grains (HSGs) are grown on the surface of the amorphous silicon
18
, so that lower electrodes
20
of cylindrical capacitors have rough surfaces (see FIG.
3
A).
A layer of thin silicon nitride
21
is deposited on the lower electrodes
20
by CVD, and a layer
22
of polycrystalline silicon doped impurities is deposited on the silicon nitride
21
. As a result, a memory cell, which is composed of a cylindrical capacitor over the MOS transistors, have been completed (see FIG.
3
B).
However, in the above-described conventional capacitor structure, there are some problems, as is described below. Stress is caused on a lower electrode surface of a cylindrical capacitor because of a nucleation of a polycrystalline silicon HSG, when a HSG rough surface is formed. The stress is centralized on the top of the cylindrical capacitor, where the grain of HSG closes together. It results that the grains on the top on the lower electrode of the capacitor are peel off and cause a short failure between neighboring capacitors.
SUMMARY OF THE INVENTION
In order to solve these problems, the present invention is provided, wherein a semiconductor memory device, which has a capacitor comprising of both the first electrode located outside of the capacitor and next to the neighboring capacitor and having grain silicon grown from amorphous silicon layer, and the second electrode formed on a semiconductor substrate, in which grain size at the top portion of the first electrode is smaller than the other portions of the first electrode. Also, in the present invention, the impurity concentration at the top portion of the amorphous silicon is higher than the other portions.
According to the present invention, there is provided a method of fabricating a semiconductor device, including forming a trench in the interlayer of semiconductor substrate, depositing impurities doped a amorphous silicon served as a lower electrode all over the trench, forming a resist so as to expose the top portion of the amorphous silicon in the trench, etching the amorphous silicon layer except for the trench, implanting impurities into the top portion of the amorphous silicon and growing HSG silicon by means of heat treatment after resist strip.


REFERENCES:
patent: 5943570 (1999-08-01), Park et al.
patent: 6090681 (2000-07-01), Yamamoto
patent: 6159785 (2000-12-01), Tsuchimoto et al.
patent: 6218230 (2001-04-01), Fujiwara et al.
patent: 6385020 (2002-05-01), Shin et al.
patent: 2000-164828 (2000-06-01), None

Affiliated with

Also associated with

Rating

Method of Fabricating a capacitor structure having... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of Fabricating a capacitor structure having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of Fabricating a capacitor structure having... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3320534