Method of fabricating a capacitor

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

Reexamination Certificate

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C438S393000, C438S210000, C438S253000, C438S239000, C438S250000, C438S381000, C438S396000, C438S488000, C438S648000, C438S655000, C438S657000, C438S682000, C438S683000, C438S684000, C438S685000, C438S664000, C257S303000, C257S304000

Reexamination Certificate

active

06340620

ABSTRACT:

FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to microcircuitry and, more particularly, to a method for fabricating a capacitor in an integrated circuit.
Integrated circuits include a variety of components. Capacitors, in particular, are common components of analog circuits, such as are found in devices such as A/D converters. The sole Figure is a schematic cross-section of one such capacitor
10
, resting on a field oxide (FOX) base
12
that in turn rests on a silicon wafer
14
. Capacitor
10
includes four layers: a bottom layer
16
of polysilicon (POLY-1), a layer of tungsten silicide (WSi)
18
, an interpoly oxide (IPO) layer
20
and a top layer
22
of polysilicon (POLY-2). (WSi being a binary metallic conductor, WSi layer
18
serves to improve the electrical conductivity of POLY-1 layer
16
. Note that although the stoichiometry of the chemical compound tungsten silicide actually is WSi
2
, tungsten silicide is commonly referred to in the art as “WSi”. In practice, the stoichiometry of layer
18
deviates from the strict 1:2 stoichiometric ratio of tungsten to silicon.) Polysilicon layer
16
and WSi layer
18
together constitute the lower plate of capacitor
10
. Interpoly oxide layer
20
constitutes the dielectric of capacitor
10
. Polysilicon layer
22
constitutes the upper plate of capacitor
10
.
Conventionally, capacitor
10
is fabricated as follows. polysilicon layer
16
is deposited by chemical vapor deposition of silane. WSi layer
18
is deposited on polysilicon layer
16
by chemical vapor deposition of tungsten hexafluoride and silane. Interpoly oxide layer
20
is deposited on WSi layer
18
by chemical vapor deposition of tetraethoxysilane (TEOS), followed by heating in a mixture of oxygen and nitrogen gases. Polysilicon layer
22
is deposited on interpoly oxide layer
20
using chemical vapor deposition of silane. Finally, capacitor
10
is heated again in ambient air to anneal WSi layer
18
. This final heating in an oxidizing atmosphere produces, as a byproduct, an oxide layer
24
that covers capacitor
10
.
SUMMARY OF THE INVENTION
According to the present invention there is provided a process for fabricating a capacitor, including the steps of: (a) depositing a first polycrystalline semiconductor layer; (b) depositing a layer of a binary metallic conductor on the first polycrystalline semiconductor layer; (c) annealing the layer of the binary metallic conductor in an oxidizing atmosphere, thereby at least partially oxidizing the layer of the binary metallic conductor; and (d) depositing a second polycrystalline semiconductor layer on the at least partly oxidized layer of the binary metallic conductor, subsequent to the annealing.
According to the present invention there is provided a process for fabricating a component of a microcircuit, including the steps of: (a) depositing a polycrystalline semiconductor layer; (b) depositing a layer of a binary metallic conductor on the polycrystalline semiconductor layer; and (c) annealing the layer of the binary metallic conductor in an oxidizing atmosphere, thereby at least partially oxidizing the layer of the binary metallic conductor, prior to any deposition of any other material on the layer of the binary metallic conductor.
According to the present invention there is provided a capacitor including: (a) a lower plate; (b) an upper plate; and (c) between the lower and upper plates, a dielectric having a refractive index, at a wavelength of 628 nm, of at most about 1.44.
According to the present invention there is provided a capacitor including: (a) a lower plate; (b) an upper plate; and (c) between the lower and upper plates, a dielectric having a charge to breakdown of at least about 10 coulombs/cm
2
.
According to the present invention there is provided a capacitor including: (a) a lower plate; (b) an upper plate; and (c) between the lower and upper plates, a dielectric having a breakdown voltage of at least about 29 volts.
The concept of the present invention is to anneal WSi layer
18
in an oxidizing atmosphere immediately after the deposition of WSi layer
18
on polysilicon layer
16
. Polysilicon layer
22
then is deposited directly on the oxide layer thus formed on WSi layer
18
. That oxide layer then serves as the dielectric of capacitor
10
, in place of interpoly oxide layer
20
that formerly was deposited by chemical vapor deposition.
The physical properties of the WSi oxide layer of the present invention are superior to those of prior art interpoly oxide layer
20
. Specifically, the WSi oxide layer has an index of refraction, at a wavelength of 628 nm, of at most about 1.44, a charge to breakdown of at least about 10 coulombs/cm
2
and a breakdown voltage of at least about 29 volts. The scope of the present invention includes a capacitor that uses the WSi oxide layer of the present invention as its dielectric. The Figure, in addition to illustrating a prior art capacitor, also serves to illustrate a capacitor of the present invention, it being understood that reference numeral
20
then refers to the WSi oxide layer of the present invention.
Although the invention is described herein in terms of a capacitor whose conductive plates are made of polysilicon and tungsten silicide, with the dielectric of the capacitor being oxidized tungsten silicide, the scope of the invention includes the fabrication of capacitors from any polycrystalline semiconductor, not just polysilicon, and of any binary metallic conductor, not just tungsten silicide.


REFERENCES:
patent: 4935380 (1990-06-01), Okumura
patent: 5208180 (1993-05-01), Gonzalez
patent: 5338701 (1994-08-01), Hsu et al.
patent: 5393691 (1995-02-01), Hsu et al.
patent: 5510637 (1996-04-01), Hsu et al.
patent: 5789289 (1998-08-01), Jeng
patent: 5804488 (1998-09-01), Shih et al.
patent: 5953599 (1999-09-01), El-Diway
patent: 6232172 (2001-05-01), Chen et al.

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