Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-05-08
2004-12-21
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S734000, C438S696000
Reexamination Certificate
active
06833327
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having a circuit consisted of a thin film transistor (hereinafter, abbreviated as TFT), and particularly, relates to a method of forming a mask in an exposure step and a method of etching using the relevant mask.
2. Description of Related Art
In recent years, an active matrix type liquid crystal display utilizing a TFT has attracted a great deal of attention. An active matrix type liquid crystal display is provided with a TFT as a switching element at each pixel.
In general, in a TFT, a channel formation region is formed with an amorphous silicon or a polycrystalline silicon. Particularly, since a TFT using a polycrystalline silicon which is fabricated particularly at a temperature of being equal to 600° C. or less (referred to as low temperature process) (hereinafter, referred to as polycrystalline silicon TFT) is capable of being formed on a glass substrate, it becomes possible to lower the cost of a semiconductor device and make the area of it larger. Moreover, in the case of a polycrystalline silicon, since the mobility of it is large, it is possible to realize a liquid crystal display in which a pixel section and a driver are integrally formed on a glass substrate.
However, if a polycrystalline silicon TFT is continuously driven, the mobility may be changed, ON-state current (current flowing in the case where a TFT is in an ON-state) may be increased, and OFF-state current (current flowing in the case where a TFT is in an OFF-state) may be increased. It is considered that this may be caused by the deterioration due to a hot carrier occurred by a high electric field nearby a drain.
In order to relax the high electric field nearby the drain and suppress the hot carrier, in the case of a MOS transistor employing the design rule of 1.5 &mgr;m or less in a gate line width, it is useful to utilize a LDD (abbreviated from Lightly Doped Drain).
For example in the case of a NMOS (n-type MOSFET) transistor, a LDD structure can be formed by providing a low concentration n-type region (n
−
region) at the edge portion of the drain utilizing a side wall of the gate side wall. The electric field nearby the drain can be relaxed by employing a LDD structure in which a concentration of impurity of drain junction is made hold a gradient.
In a LDD structure, a drain breakdown voltage can be enhanced comparing to a single drain structure. However, since the resistance of the n
−
region is large, there is a difficulty that a drain current is reduced. Moreover, since a high electric field exists immediately under the side wall, where the ionization of collision becomes the maximum, and a hot electron is injected into a side wall, the n
−
region is depleted, and further the resistance is increased, and finally a TFT is made deteriorated.
Particularly, the above-described problem becomes significant according to the reduction of the length of a channel. In order to overcome this problem in the case of a MOS transistor whose design rule is 0.5 &mgr;m or less, a Gate Overlap LDD structure which forms the n
−
region by overlapping at the edge portion of a gate electrode is useful.
Then, the employment of a Gate Overlap LDD structure has been considered in order to relax the high electric field nearby the drain not only in a MOS transistor but also in a polycrystalline silicon TFT. As for a polycrystalline silicon TFT having a Gate Overlap LDD structure, in a polycrystalline silicon layer, a channel formation region, a source region and a drain region which are high concentration regions (n
+
region), and a low concentration region (n
−
region) which has been provided between the channel formation region and the source and drain regions and which is overlapped with a gate electrode are formed.
As a method of fabricating these structures, there have been reports described in the patent document 1, the patent document 2 and the like.
Patent document 1: Japanese Unexamined Patent Publication No. 2000-349297 gazette, and
Patent document 2: Japanese Unexamined Patent Publication No. H07-202210 gazette.
PROBLEMS TO BE SOLVED BY THE INVENTION
In the step of fabricating a TFT having a Gate Overlap LDD structure, in order to form a low concentration region (n
−
region) which is overlapped with a gate electrode, it is necessary to perform the step of adding an impurity element before the formation of a gate electrode, or to add an impurity element so that the impurity element penetrates through the gate electrode.
In the case of the former method, it is necessary to utilize a mask for adding an impurity element and a mask for forming a gate electrode in the separate exposure steps. Therefore, the gate electrode and the n
−
region cannot be formed in a self-aligned process, the number of masks cannot be suppressed.
On the other hand, in the case of the latter method, it is necessary to add an impurity element only to the n
−
region after a strategy has been taken so that the impurity is not added to the channel region. Therefore, in the case where the addition of an impurity to the channel region is prevented by utilizing the gate electrode itself as a mask, it is necessary to contrive the shape of the gate electrode by thickening the gate electrode only on the channel region and so forth.
However, in order to prevent the addition of the impurity to the channel region by contriving the shape of the gate electrode, in general, the exposure step is necessarily required multiple times. Therefore, it is difficult to precisely control the shape of the gate electrode by a mask shift in the respective exposure steps, the n
−
region cannot be formed in a self-aligned process. Moreover, the number of reticles to be used is increased, and the fabrication steps become complex.
Moreover, usually, the larger the size of the resist mask becomes, the more the restraint of the conditions concerning with the patterning such as depth of focus, resist film thickness uniformity and the like becomes moderate, therefore, the process margin of the patterning step becomes larger. However, in the conventional methods, since the size and the shape of the resist mask are almost the same with the design sizes of the pattern, the more the miniaturization is progressed, the more the process margin of the patterning process is reduced, and it becomes difficult to fabricate a TFT.
For example, in the patent document 1, a method has been disclosed, in which a gate electrode having a two-layer structure is used, the step of etching a gate electrode is provided twice, and what is called a hut shape gate in which the first layer of the gate electrode is longer than the second layer in a channel length direction, is formed. Moreover, in Japanese Unexamined Patent Publication No. H07-202210 gazette, an example of a method of forming a hut shape gate in a self-aligned process has been described. A method has been described, in which the first layer of a gate electrode comprising titanium or a titanium nitride film and the second layer of a gate electrode comprising aluminum or an aluminum alloy film are formed by a DC (Direct Current) sputtering method. Subsequently, after both the first and second layers of the gate electrode have been etched by an etching treatment, only the gate electrode of the second layer is set back and processed by a side etching.
Moreover, in the technology disclosed in the patent document 2, since aluminum is used for the second layer of the gate electrode, which is different from the gate electrode such as a polycrystalline silicon having an excellent heat resistance, in the heat treatment at a high temperature, the failure due to the aluminum spike and the migration occur, there is a problem that the control of temperature is very difficult. Therefore, it is necessary to perform the activation of the impurity at a temperature at which aluminum is not denatured. However, the activation treatment after the ion injection or
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Lindsay Jr. Walter L.
Niebling John F.
Semiconductor Energy Laboratory Co,. Ltd.
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