Method of extracting parasitic capacitance values from the physi

Details Method of extracting parasitic capacitance values from the physi Method of extracting parasitic capacitance values from the physi

1995-12-01

1998-01-06

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364490, 364491, 364578, G06F 1750, G01R 2726

Patent

active

057062064

ABSTRACT:
A method of extracting parasitic capacitance values from the physical design of an integrated circuit, and more particularly, to a method of extracting lateral coupling and fringing capacitance values from the physical design of an integrated circuit, wherein the integrated circuit comprises multiple layers of conductors, each conductor having one or more lateral edges. The method comprises the steps of identifying each conductor's one or more lateral edges; fragmenting the lateral edges of each conductor into edge fragments based on a number of conductors present in layers above and/or below a given lateral edge; identifying the edge fragments which are laterally adjacent to each edge fragment; computing one or more relationships between an edge fragment and each of its laterally adjacent edge fragments; retrieving parasitic capacitance data for each edge fragment; and using the retrieved parasitic capacitance data to compute one or more parasitic capacitance values for each edge fragment. Disadvantages of prior methods are overcome in that extracted lateral coupling capacitances are based on the presence of conductors running above and/or below a given lateral conductor edge, and fringing capacitances are based on the spacing between a given lateral conductor edge and a laterally adjacent conductor edge.

REFERENCES:
patent: 5452224 (1995-09-01), Smith, Jr. et al.
patent: 5568395 (1996-10-01), Huang
Simsek et al., "Laxter, a new method for extraction of parasitic effects from MCM layout", IEEE, pp. 344-347, Apr. 1994.
Gannett, "Extending an FET layout verification system to bipolar technology", IEEE, Proceedings of 1988 Bipolar Circuits and Technology Meeting, pp. 183-186, Sep. 12, 1988.
Chang, "Analytical IC Metal-Line Capacitance Formulas", IEEE Transactions on Microwave Theory and Techniques, pp. 608-611, Sep. 1976.
Chung et al., "3-D Interconnect Capacitance Calculation for Multi-conductor and its Application to a ROM Circuit Design", Proceedings of Fifth Annual IEEE International ASIC Conference and Exhibit, pp. 475-478, Sep. 21, 1992.
Ruehli et al., "Efficient Capacitance Calculations for Three-Dimensional Multiconductor Systems", IEEE Transactions on Microwave Theory and Techniques, vol. MTT-21, No. 2, pp. 76-82, Feb. 1973.

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