Method of extracting parameters for circuit simulation

Details Method of extracting parameters for circuit simulation Method of extracting parameters for circuit simulation

1993-01-19

1996-02-06

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

054900956

ABSTRACT:
In extracting parameters for use in circuit simulation of an IC device having a plurality of insulated gate field-effect transistors (IGFETs), layout data for patterns for the IC device are prepared. The patterns include gate patterns for the IGFETs, at least one of which is a bent gate pattern such that drain and source regions are defined on opposite sides of the bent gate pattern. An index symbol data is added to the layout data, which is for the bent gate pattern, to thereby form designed pattern data. For higher accuracy of the circuit simulation, the index symbol data in the designed pattern data is detected and used to produce parameters concerning the gate patterns for the IGFETs, thereby contributing to determination of a capability of controlling electric current in the IGFETs.

REFERENCES:
patent: 5210699 (1993-05-01), Harrington
patent: 5247456 (1993-09-01), Ohe et al.
patent: 5278770 (1994-01-01), Gore et al.
"Automated Extraction of SPICE Circuit Model from Symbolic Gate Matrix Layout with Printing" by Freeman et al., IEEE 23rd Design Automation Conf., 1986, pp. 418-424.
"Resistance Extraction in a Hierarchical IC Artwork Verification System" by Mori et al., IEEE 1985, pp. 196-198.
"LAS: Layout Pattern Analysis System with New Approach" by Okamura et al., IEEE 1982, pp. 308-311.
IEEE 1987 Custom Integrated Circuits Conference, pp. 133-136.

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