Measuring and testing – Frictional resistance – coefficient or characteristics
Reexamination Certificate
1999-02-19
2003-05-27
Patel, Harshad (Department: 2855)
Measuring and testing
Frictional resistance, coefficient or characteristics
C324S662000
Reexamination Certificate
active
06568243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for and a method of evaluating surface irregularity, and more particularly to an apparatus for and a method of evaluating the surface irregularity, wherein the surface of an amorphous silicon film provided with hemispherical grains is monitored in degree of surface irregularity.
The present application claims the priority of Japanese Patent Application No. Heisei 10-037454 filed on Feb. 19, 1998, which is hereby incorporated by reference.
2. Description of the Related Art
In recent years, an integrated circuit of silicon semiconductors, particularly, DRAM (i.e., Dynamic Random Access Memory) shows in general a tendency to higher integration. As the higher integration of the semiconductor circuit reduces an effective area for forming a capacitor, various attempts have been made so as to increase an electrode area by modifying in structure the capacitor.
For example, H. Watanabe et. al have proposed a method for increasing a surface by forming hemispherical grains (i.e., HSG-Si: Hemispherical Grain Silicon) in a surface of an electrode, as disclosed in the following document: “A new stacked capacitor structure using hemispherical-grain polysilicon electrode”, 22nd Conference on Solid State Device and Materials p. 873, 1990. A technique for forming the HSG-Si mentioned above is a technique for increasing a surface area by producing geometrical irregularity in a clean surface of a silicon layer through thermal, migration of silicon atoms to such surface.
FIG. 11
is a cross-sectional view of a DRAM, which includes a capacitor provided with a stacked electrode having the HSG-Si formed in its electrode surface. As shown in the same drawing, the DRAM is constructed of: an interlayer insulation film
109
of a device forming substrate
117
, formed in which are an insulated-gate field effect transistor, a bit line
108
and a word line
104
b
; and, a capacitor
118
, an interlayer insulation film
114
, an aluminum wiring
115
and a cover insulation film
116
all of which are sequentially stacked together in the order of mention. The capacitor
118
is brought into contact with a source/drain diffusion region
105
a
through a contact hole
110
passing through both the interlayer insulation films
106
,
109
of the device forming substrate
117
. Incidentally, the device forming substrate
117
is constructed of: an SOI (Semiconductor On Insulator) substrate
101
in which a device forming semiconductor layer
3
is formed on a support substrate
1
; a device separating insulation film
102
formed on the SOI substrate
101
; a gate insulation film
103
and a gate electrode
104
a
both disposed above the device forming semiconductor layer
3
; a gate (word) wiring
104
b
disposed, over the device separating insulation film
102
; a pair of the source/drain diffusion regions
105
a
,
105
b
disposed in opposite sides of the gate electrode.
104
a
; the interlayer insulation film
106
covering these source/drain diffusion regions
105
a
,
105
b
; the bit line
108
brought into contact with the source/drain diffusion regions
105
b
through the contact hole
107
Of the interlayer insulation film
106
; and, the interlayer insulation film
109
disposed on the bit line
108
.
The capacitor
118
is constructed by sequentially stacking together a stacked electrode
111
of an amorphous silicon (a-Si) film
4
, a capacitance insulation film
112
and a counter electrode (cell-plate electrode)
113
in the order of mention. Formed in the surface of the a-Si film
4
of the stacked electrode
111
are hemispherical grains
5
.
In fabricating the capacitor
118
described above, at first, the device forming substrate
117
is produced.
Then, as shown in FIG.
12
(
b
) the contact hole
110
is formed in the interlayer insulation films
106
,
109
so as to reach an upper portion of the source/drain diffusion region.
105
a
. Subsequent to this, the a-Si film
4
a
which is brought into contact with the source/drain diffusion region
105
a
through the contact hole
110
is formed using a low pressure CVD process. After that, as shown in FIG.,
13
(
a
), the a-Si film
4
a
is subjected to a pattering process to assume the same shape as that of the stacked electrode
111
. Then, the a-Si film
4
thus assuming the same shape as that of the stacked electrode
111
is heated under a reduced pressure, subjected to a Si
2
H
6
gas in this condition, and then subjected to a nitrogen gas. Due to this, as shown in FIG.
13
(
b
), the hemispherical grains
5
are formed in the surface of the a-Si film
4
so that the stacked electrode
111
is produced. Subsequent to this, both the capacitance insulation film
112
and the counter electrode
113
are formed on the stacked electrode
111
so that the capacitor
118
is produced. After that, through the conventional predetermined process steps, the DRAM as shown in
FIG. 11
is produced.
In mass-producing the DRAM mentioned above, in order to reproduce a predetermined capacitance value of the capacitor
18
, it is very important to evaluate the degree of irregularity of the surface of the a-Si film
4
immediately after the formation of the hemispherical grains
5
in the above surface.
Heretofore, as a method for evaluating the degree of irregularity of the surface, it has been known to measure the capacitance value of the capacitor actually produced by forming both the capacitance insulation film and the counter electrode on the stacked electrode
111
after the formation of the hemspherical grains
5
. Further, it has been also known to monitor the irregularity of a surface of a test specimen through reduction in reflectance by measuring the reflectance of white light having been incident on the surface of the test specimen having the irregularity. In a further another conventional method, the degree of irregularity of the surface of the test specimen is evaluated through reduction in reflectance by measuring a secondary X ray with the use of a detector disposed in the side of reflection in a condition in which a monochromatic X ray is incident on the surface of the specimen at an angle of less than a critical angle, and, therefore totally reflected (see Japanese Patent Laid-Open Application No. Hei4-15933). In a still further another conventional method, as shown in FIG.
14
(
b
), a light beam having a wavelength of less than 500 nm is incident on a surface of a test specimen, the surface being provided with irregularity. After that, as shown in FIG.
14
(
a
), the light reflected from the above surface is measured in intensity to evaluate a capacitance value of a capacitor (see Japanese Patent Laid-Open Application No. Hei8-254415).
The conventional method, in which the degree of the irregularity of the surface of the test specimen is evaluated by measuring the capacitance value of the capacitor actually produced, is the most reliable method. However, in such conventional method, it is necessary to form the capacitance insulation film by deposition, and further necessary to form the counter electrode after the formation of the hemispherical grains (i.e., HSG-Si: Hemispherical Grain Silicon). Due to this, patterning of both the counter electrode and an extension for use in measurement is required, which causes the inconvenience of taking too much time and labor. Consequently, the conventional method is not very suitable for monitoring the surface irregularity in mass production.
On the other hand, another one of the conventional methods which uses the white light to measure the reflectance is simple, and, therefore suitable for monitoring the surface irregularity in mass production. However, when such conventional method is used as to the a-Si film, since the light used is visible light, the light passes through the silicon and is reflected at a boundary surface between the a-Si film and a film to produce, a reflected light. This reflected light varies intensity, depending on the optical properties of the material under the a-Si film. In
NEC Corporation
Patel Harshad
Sughrue & Mion, PLLC
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