Method of evaluating a MIS-type semiconductor device

Details Method of evaluating a MIS-type semiconductor device Method of evaluating a MIS-type semiconductor device

1995-09-27

1997-12-23

Karlsen, Ernest F.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324769, 437 8, G01R 3100, H01L 2100

Patent

active

057010889

ABSTRACT:
A method of evaluating a MIS-type semiconductor device which comprises an insulative layer(s) and a conductive layer (s) formed one after another on a semiconductor substrate wherein: using a sample with an interface trapped charge density of 1.times.10.sup.10 /cm.sup.2 .multidot.eV or less and a mobile ionic charge density of 3.times.10.sup.10 /cm.sup.2 or less in said insulative layer, said MIS-type semiconductor device is treated by applying a positive or negative voltage in the range of 1-5 MV/cm between said semiconductor substrate and said conductive layer at a temperature of 100.degree.-300.degree. C. and maintaining this voltage for 1-60 minutes (hereafter referred to as "BT treatment"); before and after said BT treatment, the capacitance-voltage characteristics (hereafter referred to as "C-V characteristics) of said MIS-type semiconductor device are measured at room temperature; and the carrier trap density of said insulative layer is determined based on the shift of the flat band voltage of said C-V characteristics from before to after said BT treatment.

REFERENCES:
patent: 4978915 (1990-12-01), Andrews, Jr. et al.

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