Patent
1995-03-28
1997-09-23
Lall, Parshotam S.
395500, 39518401, G06F 9455
Patent
active
056714025
ABSTRACT:
Correct and accurate evaluation as to which portion of a program to be subjected to rate performance evaluation takes much time is disclosed. Program counters (101c, 101d) hold instructions in simulation of a simulation engine (101). An instruction execution count and a cumulative clock cycle count required for the execution are arranged for the same instruction and stored in an execution count storage array (102b) and a cumulative clock cycle count storage array (102c), respectively. The execution count of the same instruction and the cumulative time required for the execution thereof are determined.
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patent: 5517629 (1996-05-01), Boland
Nasu Takashi
Sakamoto Tadashi
Lall Parshotam S.
Mitsubishi Denki & Kabushiki Kaisha
Vu Viet
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