Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-08-11
2001-06-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S052000, C438S421000, C438S735000, C257S417000
Reexamination Certificate
active
06242363
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to semiconductor structures and, more particularly, to methods of etching a semiconductor wafer using a sacrificial wall and structures formed thereby.
BACKGROUND OF THE INVENTION
Semiconductor technology has driven rapid advancements in many disciplines across numerous industries. Semiconductor technology has facilitated the fabrication of highly complex and compact integrated circuit (IC) devices. Semiconductor technology has also facilitated the manufacture of microelectromechanical systems (MEMS). At present, advancements are being made to facilitate the fabrication of MEMS in integrated circuits on a common substrate.
During the fabrication of the above devices, numerous structures are typically formed on a semiconductor wafer. These structures may, for example, be formed on the semiconductor substrate itself or on another layer formed over the semiconductor substrate. As used herein, the term wafer layer will be used to refer to any layer on a semiconductor wafer, including the substrate itself and overlying layers. The structures may include gate electrodes and trenches, commonly found on integrated circuit devices, and mirrors, gears and comb fingers, commonly found on MEM systems.
Many of the structures found on IC devices and MEM systems are deep and narrow and/or narrowly spaced and can benefit from having smooth and/or vertical sidewalls. Narrow structures allow device sizes to be scaled down. Smooth and vertical sidewalls can for example increase the durability and reliability of a structure. This, in turn, can increase the life span of the structure and can increase fabrication yield. Smooth and vertical side walls can also improve the operating characteristics of a structure. For example, smooth and vertical side walls of a mirror can improve the optical transmission properties of an optical switch. As a result, manufacturers continue to seek techniques for improving the smoothness and/or verticality of narrow and deep structures formed on semiconductor wafers.
SUMMAIY OF THE INVENTION
The present invention provides techniques for forming relatively vertical structures on a semiconductor wafer. A vertical structure may be a sidewall of a mirror or actuator beam of a MEMS device, for example.
One embodiment of the invention is a method for forming a raised structure on a semiconductor wafer. In the method, a patterned masking layer is formed over a wafer layer. The patterned masking layer typically includes a first mask covering a first region of the wafer layer and at least one side mask adjacent to the first mask, covering a side region of the wafer layer. After forming the patterned masking layer, exposed portions of the wafer layer adjacent the masks are removed using the patterned masking layer. This leaves a first raised structure (relative to an adjacent removed area) in the first substrate region and a sacrificial raised structure in the side region adjacent the first raised structure. After removing the exposed portions of the wafer layer, the sacrificial raised structure is selectively removed while leaving the first raised structure intact. The sacrificial raised structure and overlying side mask typically reduce the area of the wafer layer which would otherwise be exposed during the removal. This facilitates the formation of the vertical sidewall on the raised structure.
This method may be used to form a structure in a wafer layer, such as a silicon substrate, having an underlying insulating layer. In this case, the method may further include removing exposed substrate regions surrounding the side region to leave the sacrificial raised structure on the insulating layer isolated from the first raised structure. The sacrificial raised structure may then be removed by removing the insulating layer from beneath the sacrificial raised structure, thereby freeing this structure from the substrate. This may, for example, be performed by dipping the semiconductor wafer in an etching solution such that the sacrificial raised feature falls into the etching solution when the underlying insulating layer is sufficiently removed. While the insulating layer may be removed, at least in part, from beneath the first raised structure, the first raised structure may be supported via another portion of the wafer layer under which the insulating layer remains.
A semiconductor wafer, in accordance with an embodiment of the invention, includes a wafer layer defining a structure having a sidewall separated, in a direction normal to the sidewall, from the wafer layer by at least 50 microns and having a verticality of at least 90±0.6 degrees. The verticality is measured with respect to a horizontal plane of the semiconductor wafer.
The above summary of the invention is not intended to describe each illustrated embodiment or every implementation of the invention. The figures in the detailed description which follow more particularly exemplify these embodiments.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
FIGS. 1A-F
and
2
A-B illustrate an exemplary process in accordance with one embodiment of the invention; and
FIGS. 3A-3G
illustrate an exemplary process in accordance with another embodiment of the invention.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
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ADC Telecommunications Inc.
Malsawma Lex H.
Merchant & Gould P.C.
Smith Matthew
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