Method of etching a lateral trench under a drain junction of...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S627000, C438S198000, C438S296000

Reexamination Certificate

active

07023068

ABSTRACT:
In a MOS transistor, the drain capacitance is reduced by forming a lateral trench underneath the drain. This is typically done by using an anisotropic wet etch process in a <110> direction of a <100> orientation wafer.

REFERENCES:
patent: 4523213 (1985-06-01), Konaka et al.
patent: 4638552 (1987-01-01), Shimbo et al.
patent: 4685198 (1987-08-01), Kawakita et al.
patent: 6404034 (2002-06-01), Widmann et al.
patent: 6429091 (2002-08-01), Chen et al.
patent: 6621123 (2003-09-01), Nakabayashi et al.
patent: 6830980 (2004-12-01), Mansoori et al.

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