Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data
Reexamination Certificate
1998-11-03
2002-04-02
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Synchronizing the sampling time of digital data
C348S021000
Reexamination Certificate
active
06366629
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a method of time aligning symbol data in a digitally modulated transmission system and more specifically to estimating symbol timing phase and rate offsets of a sampled digitally modulated signal having repetitive symbol sync sequences, such as 8-VSB digital television signals.
The Federal Communications Commission has adopted the Digital Television Standard developed by the Advanced Television Systems Committee (ATSC). The Digital Television Standard is designed to transmit high quality video, audio and ancillary data over a 6 MHz channel. The Standard describes the channel coding and modulation RF/transmission subsystems for terrestrial and cable applications. The modulation subsystem uses a digital data stream to modulate the transmitted signal and may be implemented in two modes: a terrestrial broadcast mode (8-VSB) delivering about 19 Mbps, and a higher data rate mode (16-VSB) delivering about 38 Mbps for cable televisionvystems where higher signal to noise is ensured.
The modulation technique implemented in the Digital Television Standard was developed by Zenith Corp. and employs vestigial sideband modulation. The overall system response of the transmitter and receiver filtering corresponds to a raised cosine filter to avoid system generated intersymbol interference. The system response is implemented with serially coupled, nominally identical root raised cosine filters in the transmitter and in the receiver.
The incoming digital data stream is randomized, forward-error-correction (FEC) encoded and interleaved. The randomized, FEC coded and interleaved data is trellis encoded as an 8-level (3-bit) one dimensional constellation. The outputs of the trellis coder are mapped into symbols that are one of eight symmetric odd-valued integer levels from −7 to +7 units. To aid synchronization in low signal to noise and/or high multipath situations, segment and field syncs are inserted in the 10.76 Msymbols/sec symbol stream. A small pilot tone is added as well at the carrier frequency generated by offsetting the real or I channel of the complex signal containing the data and the sync pulses by 1.25 units. The offset causes the pilot tone to be in-phase with the I channel signal component. At the transmitter, the composite signal passes through a root raised cosine filter and modulates an intermediate frequency carrier signal which is up-converted to an RF frequency for transmission at the desired channel frequency. Alternately, the composite signal may be used to directly modulate the RF carrier.
Referring to
FIG. 1
, there is shown a representative block diagram of a VSB receiver for extracting the digital television signal data from the digitally modulated RF signal as described in the “Guide to the Use of the ATSC Digital Television Standard” published by the ATSC. The receiver
10
receives the UHF or VHF signal through a band-pass filter and broadband tracking filter
12
. A wideband amplifier
14
increases the signal level and couples it to a first mixer
16
. The mixer is driven by a
1
st local oscillator
18
that tunes over a range from 978 to 1723 MHz. The 1 st local oscillator
18
is synthesized by a phase locked-loop and controlled by a microprocessor (not shown). The output of the mixer
16
is an up-converted intermediate frequency (IF) signal at 920 MHz. The IF signal is coupled to an LC filter
20
in tandem with a band-pass ceramic resonator filter
22
centered at 921 MHz. An IF amplifier
24
is placed between the two filters. The IF signal is coupled to a second mixer
26
that is driven by 2nd local oscillator
28
. The
2
nd local oscillator
28
is an 876 MHZ voltage controlled SAW oscillator controlled by a frequency and phase-locked loop (FPLL) synchronous detector
30
. The output of the second mixer
26
is centered at 45 MHz. This IF signal drives a constant gain 44 MHZ amplifier
32
. The output of the amplifier
32
is coupled to an IF SAW filter
34
. The IF SAW filter
34
implements an approximation of the transmission system's root raised cosine filter at the receiver. The output of the SAW filter
34
is coupled to the FPLL synchronous detection circuitry
30
via an AGC controlled amplifier
36
.
Carrier recovery is performed on the pilot signal by the FPLL circuit
30
. The operation of this circuit is described in U.S. Pat. No. 4,091,410, assigned to Zenith Corp. The configuration provides a Phase Locked Loop (PLL) function with a very wide pull-in range which insures rapid carrier acquisition. The I channel baseband data signal from the synchronous detector
30
is coupled through a low pass filter
54
to an analog-to-digital converter (A/D)
56
that is clocked by a properly phased 10.76 MHz symbol clock
58
. The digital data from the A/D converter
56
is coupled to a data segment sync detector
60
having a narrow bandwidth filter for detecting from the synchronously detected random data the repetitive data segment syncs as described in U.S. Pat. No. 5,416,524, assigned to Zenith Corp. The symbol clock generator
58
free runs at a rate reasonably close to the transmitted symbol clock prior to phase locking. The data segment sync detector
60
, containing a 4-symbol sync correlator
62
, looks for the sync symbols occurring at the specified sync repetition rate. The output of the correlator is integrated using a segment delay line
64
, with only the syncs rising to a high level, since all the other data is guaranteed to be random in nature. The clock frequency need not be locked to find the segment sync in order to recognize the segment sync. Clock phasing begins when a sync detector/confidence counter
66
reaches a predefined level indicating that the segment sync has been found. The sync detector signal from the sync detector/confidence counter
66
samples a quadrature filter
68
output during the sync time in a sampler/phase detector
70
, producing an error voltage proportional to the phase difference between the receiver's clock sampling time and the zero crossing of the quadrature filter
68
output, which corresponds to a maximum eye opening. The 4-tap quadrature filter
68
converts the segment syncs into “discriminator S-curve” signals. The sampler
70
output is coupled through an APC low pass filter
72
for adjusting the symbol clock generator
58
either higher or lower in frequency, until the proper sampling time is reached, with the symbol clock locked to the incoming data clock frequency.
A Hewlett-Packard HP 89440A Vector Signal Analyzer has been used for making measurements on 8-VSB signals. The HP 89440A includes a superheterodyne receiver having a first LO and mixer for up-converting the incoming signal to a first IF frequency. Second and third LOs and mixers respectively generate second and third IF frequencies of 40 MHz and 10 MHz. The 10 MHz IF is digitized by an analog-to-digital converter with the digitized data being down converted to baseband real and imaginary data. The real and imaginary data values are passed to a digital signal processor for FFT conversion and additional signal processing. A limitation of a superheterodyne type receiver is the need for bandwidth limiting filters between the IF stages to prevent the undesired mixer signal outputs from entering subsequent IF stages. Such filtering can mask artifacts in the transmitter signal resulting in inaccurate measurements of the operating condition.
In certain applications, such as measurements of the signal quality, a software based demodulator could be used to demodulate the received IF signal. A software based demodulator can bring greater flexibility in processing the digitally modulated signal. For example, in some measurements, it is desirable to limit the amount of signal filtering to prevent the masking of desirable characteristics in the signal. This would include narrow band-limiting filters in the IF signal. channel and the transmission system's receiver filter. In other cases the demodulator has to provide signal samples representative
Chen Xiaofen
Kuntz Thomas L.
Bucher William K.
Gray Francis I.
Pham Chi
Tektronix Inc.
Tran Khai
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