Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-03-07
2003-09-02
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
C438S068000, C438S113000, C438S460000
Reexamination Certificate
active
06613591
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to surface characteristics of semiconductor wafers, and more particularly to predicting the future waviness of a semiconductor wafer based upon its surface characteristics after cutting but before lapping and polishing.
Semiconductor wafers used as starting materials for the fabrication of integrated circuits must meet certain surface flatness and waviness requirements. Such wafers must be particularly flat and free of waviness for printing circuits on them by, for example, an electron beam-lithographic or photolithographic process. The quality of the wafer surface directly influences device line width capability, process latitude, yield and throughput. The continuing reduction in device geometry and increasingly stringent device fabrication specifications force manufacturers of semiconductor wafers to prepare increasingly flatter and defect free wafers.
Semiconductor wafers are generally prepared from a single crystal ingot cut, or sliced, into individual wafers. This cutting process may leave surface defects in the cut wafers, one of which is waviness, the focus of the present invention, as will be discussed in greater detail below. The slicing process and apparatus, and developments therein, are more fully described in the attached provisional application filed simultaneously by Milind Bhagavat, Dale A. Witte, Steven L. Kimbel, David Alan Sager and John Peyton entitled METHOD AND APPARATUS FOR SLICING SEMICONDUCTOR WAFERS. After cutting, the wafers are subjected to several processing operations to reduce the thickness of the wafer, remove damage caused by the cutting operation, and create a highly reflective surface. In conventional wafer shaping processes, a lapping operation is performed on the front and back surfaces of the wafer using an abrasive slurry and a set of rotating lapping plates. The lapping operation reduces the thickness of the wafer to remove surface damage induced by the cutting operation and to make the opposing side surfaces of each wafer flat and parallel. Upon completion of the lapping operation, the wafers are subjected to a chemical etching operation to reduce further the thickness of the wafer and remove mechanical damage produced in the prior processing operations. At least one surface of the wafer may then be polished (both surfaces of each wafer may also be double-side polished) to improve wafer flatness and remove previous wafer damage. Even with such a damage-free surface, however, the wafer may not meet production specifications because it exhibits an unacceptable amount of waviness.
As the features included in integrated circuits become smaller, global nanotopography of silicon wafers becomes even more important. Waviness is one type of nanotopography feature observed in polished wafers. Typically, the direction of this waviness feature corresponds with the cutting direction of the cutting wire. Waviness is an unwanted artifact of wiresaw cutting that often survives downstream processing. Such wafer waviness exists at wavelengths across a spectrum, from large to small. Previous work related to the influence of the slicing process on wafer nanotopography focused on warp, such as site warp, or local warp, within particular wafer sites (e.g., U.S. Pat. No. 6,057,170). Such site specific measurement and analysis focuses on small wavelength warp and does not capture longer wavelength warp, such as those from about 50 millimeters (2.0 inches) to about 80 millimeters (3.1 inches) in length, which are defined as waviness herein. Focusing on site warp does not provide a comprehensive waviness solution because it does not take into account the free shape of the wafer. In contrast, waviness is directly related to the free shape of the wafer because it comprises the medium wavelength surface features of as-cut wafers. These medium wavelength features are between about 50 millimeters (2.0 inches) and about 80 millimeters (3.1 inches) on a 200 millimeter (7.9 inch) diameter wafer. For the present invention, such waviness is defined in the cutting direction, because waviness occurs primarily in that direction. The methodology, however, is more generally applicable to analysis in any direction where waviness is exhibited (e.g., waviness developed by other processing steps).
Recently, a number of new measurement tools have become available that are capable of capturing post-polish profiles of wafers as nanotopography features (e.g., WIS CR83-SQM®, available from ADE Corporation of Westwood, Mass., U.S.A., NanoMapper®, available from ADE Corporation and Magic Mirror™ available from HOLOGENiX of Huntington Beach, Calif., U.S.A.). Because these instruments use optical principles for surface characterization, they are capable of recognizing nanotopography features, but are incapable of identifying waviness of rough, as-cut wafers.
As-cut wafers, those wafers that are sliced from the ingot but not yet polished, that exhibit waviness may ultimately polish into either an acceptable wafer shape or an unacceptable wafer shape. There is no method, however, capable of predicting which wafers will polish into an acceptable shape and which will not. Because the steps between wafer cutting and polishing are time-consuming and costly, a method that could predict whether an as-cut wafer would include waviness after polishing would allow for selective polishing of wafers, thereby saving the expense of polishing wafers that would not ultimately produce a desired result. The method of the present invention achieves such a result.
SUMMARY OF THE INVENTION
Among the several objects of this invention may be noted the provision of such a method that estimates the post-polishing waviness of a wafer from data gathered in an as-cut condition; the provision of such a methodology that speeds the reaction time to identify a poorly performing wafer cutting process; the provision of such a methodology that identifies potentially problematic wafers for removal from the production stream before lapping and polishing; the provision of such a methodology that is proactive by actively seeking to identify problematic wafers earlier in the wafer production process; and the provision of such a methodology that creates a bright-line specification for predicting unacceptable waviness.
A method for estimating the post-polish waviness of an as-cut semiconductor wafer comprises measuring a thickness profile of an upper surface of a semiconductor wafer along an angle of the wafer and measuring a thickness profile of a lower surface of the wafer along the angle. A median surface profile of the wafer is constructed from the measurements. A band-pass filter is applied to the median surface profile to form a filtered median surface profile. A warp measurement of the filtered median surface profile is compared to a specification selected to estimate post-polish waviness.
In another embodiment, a method of producing wafers cut from stock material which are capable of meeting a predetermined flatness specification after further processing of the wafers is disclosed. The method comprises cutting the stock material to form multiple wafers and measuring at least one of the wafers to establish a surface profile of the wafer. The surface profile is filtered to produce a filtered surface profile which eliminates at least some of the features of the surface profile. The maximum deviation of the filtered surface profile is determined and compared against a maximum deviation standard. Only those wafers which have a maximum deviation less than the maximum deviation standard are processed further.
Other objects and features will be in part apparent and in part pointed out hereinafter.
REFERENCES:
patent: 5376890 (1994-12-01), Keevil et al.
patent: 6057170 (2000-05-01), Witte
patent: 971 399 (2000-01-01), None
Anderson Gary L.
Bhagavat Milind S.
Teasley Brent F.
Xin Yun-Biao
MEMC Electronic Materials , Inc.
Nelms David
Nhu David
Senniger Powers Leavitt & Roedel
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