Method of estimating lifetime of semiconductor device, and...

Details Method of estimating lifetime of semiconductor device, and... Method of estimating lifetime of semiconductor device, and...

2001-06-11

2003-04-01

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

With measuring or testing

C438S017000, C324S762010

Reexamination Certificate

active

06541285

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of estimating a lifetime concerning hot carrier degradation of a MOS transistor, more specifically, it relates to improvement of accuracy in lifetime estimation. The present invention relates to also a method of simulating circuit characteristic degradation caused by hot carrier degradation of a MOS transistor, more specifically, it relates to improvement of simulation accuracy.
BACKGROUND OF THE INVENTION
The size of MOS transistors has been reduced considerably with a trend toward high density, high integration and miniaturization of semiconductor integrated circuit devices. With the miniaturization trend, especially due to the decreasing channel length, hot carrier degradation has been a critical problem, since the degradation will affect the reliability of a MOS transistor. Hot carrier degradation refers to a phenomenon that highly energized electrons and positive holes (hereinafter ‘hot carrier’) are generated by a high electric field at a drain end of a MOS transistor, which will degrade the characteristics of a gate oxide film. This hot carrier degradation includes plural degradation modes. When the degradation relates to a condition to cause a maximum substrate current, a drain current is decreased over time for any of N-type or P-type MOS transistor. As a result, the delay time of the circuit is increased over time. When the delay reaches a certain degree, a timing error occurs at a time of input/output of signals in the interior of the semiconductor integral circuit or between the circuit and outside, and this causes malfunction of an entire system in which the semiconductor integrated circuit is assembled.
Regarding the hot carrier degradation, hot carrier reliability has been evaluated by a stress acceleration experiment under a DC condition with respect to the MOS transistor. And product reliability has been provided by optimizing a production process to satisfy the hot carrier evaluation standard.
A hot carrier lifetime model used in such a hot carrier reliability evaluation is as follows. Hot carrier degradation of a MOS transistor is evaluated by, for example, &Dgr;I
d
/I
d
, and this is a ratio of a drain current variation &Dgr;I
d
to an initial drain current I
d
. Under a static hot carrier stress condition by a DC (direct current), the hot carrier degradation rate &Dgr;I
d
/I
d
is represented by the following formula (1).
&Dgr;I
d
/I
d
=A·t
n
  (1)
Here, t denotes a hot carrier stress time, while characters ‘A’ and ‘n’ are regarded as coefficients depending on a transistor manufacturing process and a stress condition.
If a transistor lifetime &tgr; is defined as a stress time required for a variation rate of drain current to reach (&Dgr;I
d
/I
d
)
f
, a formula (2) is obtained from the formula (1). For example, time t when (&Dgr;I
d
/I
d
)
f
=10% is defined as a lifetime &tgr;.
(&Dgr;
I
d
/I
d
)
f
=A·&tgr;
n
  (2)
In a typical stress acceleration experiment for a MOS transistor, DC stress is applied to a transistor so that the transistor lifetime reaches a variation rate (&Dgr;I
d
/I
d
)
f
defined by the formula (2) within a measureable time period, that is, from 1 second to about 100,000 seconds. Then, a drain current of the transistor is measured to calculate a transistor lifetime from &Dgr;I
d
/I
d
in a linear region or a saturation region.
The following stress voltage application method is used in a stress acceleration experiment during a hot carrier reliability evaluation. Every gate voltage V
g
is determined at a condition where the hot carrier degradation rate is maximized with respect to each of plural drain voltages V
d
used for the acceleration experiment. In other words, each of the gate voltages V
g
causes a maximum substrate current I
sub
under a respective drain current. At this time, one gate voltage is set for each drain voltage. In this way, a transistor lifetime is calculated under a condition that the degradation rate is maximized with respect to an arbitrary drain voltage.
A method of evaluating hot carrier reliability of a MOS transistor is described in IEEE Electron Device Lett., vol. 4, pp. 111-113, April 1983 by E. Tanaka et al. According to the description, the lifetime &tgr; of a MOS transistor is calculated by using an empirical model represented by the following formula (3).
&tgr;∝(
I
sub
/W
)
−m
  (3)
In this formula, W denotes a gate width and I
sub
denotes a substrate current.
FIG. 6
shows a method of estimating a lifetime based on this empirical model. In
FIG. 6
, each black dot
21
denotes a measured value of the lifetime, and a line
22
denotes a regression line of lifetime estimation. Numeral
23
denotes a maximum substrate current value for a unit gate width in actual use, and
24
denotes an estimated lifetime in actual use. For a lifetime estimation, a logarithm of I
sub
/W is used to enter a horizontal axis of a graph, and a logarithm of T is used to enter the vertical axis so that the measured values
21
for a lifetime are plotted. Next, the regression line
22
is fitted to the measured values
21
by using a least squares method. The maximum substrate current
23
for a unit gate width in actual use is also measured separately. The preliminary fitted regression line
22
is used to obtain a lifetime
24
corresponding to the maximum substrate current
23
in actual use, and this is determined as an estimated lifetime in actual use. Hot carrier reliability evaluation is executed by observing whether the lifetime
24
satisfies a hot carrier evaluation standard, e.g., whether the lifetime
24
satisfies a standard of at least 10 years.
Recently however, such a conventional hot carrier evaluation standard has been difficult to satisfy in the hot carrier reliability evaluation under the DC condition. For solving this problem, a recently developed technique provides product reliability by a simulation of hot carrier degradation for a semiconductor integrated circuit (hereinafter “circuit reliability simulation”). A circuit reliability simulator simulates a circuit operation subsequent to hot carrier degradation by using a hot carrier lifetime model and a SPICE parameter after degradation, and the simulation is based on calculated values of voltage and current at every terminal of every transistor which are calculated by a circuit simulator SPICE. Typical simulators are BERT developed at the University of California, Berkeley (R. H. Tu et al., “Berkeley reliability tools-BERT,” IEEE Trans. Compt.-Aided Des. Integrated Circuits & Syst., vol.12, no.10, pp.1524-1534, October 1993), and BTABERT (a commercial version of BERT). This circuit reliability simulation technique is used for estimating degraded or malfunctioning parts in a semiconductor integrated circuit and measures against the degradation or malfunction are taken during designing, so that reliability assurance or reliability design is possible.
An example of simulation methods concerning hot carrier degradation of a MOS transistor is described in IEEE Trans. Electron Devices, vol.35, pp.1004-1011, July 1988 by Kuo et al. A hot carrier lifetime model applied to this circuit reliability simulator is as follows. According to Kuo et al., a lifetime &tgr; of a MOS transistor is represented by an empirical formula (4) using a hot carrier lifetime model.
&tgr;=((&Dgr;
I
d
/I
d
)
f
)
1

·H·W·I
sub
−m
·I
d
m−1
  (4)
In the formula, W denotes a gate width, H denotes a coefficient depending on a condition for manufacturing a transistor, I
sub
denotes a substrate current, and m denotes an index relating to an impact ionization and interface level formation.
A coefficient A in a hot carrier lifetime model is represented by a formula (5) that is derived from the formulas (2) and (4).
A=
((
W·H
)
−1
·I
sub
m
·I
d
1−m
)
n
  (5)
Therefore, a formula (6) is derived from the formulas (1) and (5).
&Dgr;I
d
/I
d
=((
W·H
)
−1
·I
sub
m
·I
d
1−m
·t
)
n
  (6)
Whe

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