Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
1996-09-06
2001-01-09
Stamber, Eric W. (Department: 2765)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S117000, C324S762010, C438S014000, C438S017000
Reexamination Certificate
active
06173235
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods of estimating the lifetime of a transistor degraded by hot carriers in an MOSFET and, more particularly, to a method of estimating the lifetime of a floating SOI-MOSFET.
2. Description of the Background Arts
In a bulk MOSFET, the lifetime of the transistor degraded by hot carriers can be estimated by measuring a substrate current Isub.
FIG. 21
schematically shows a cross sectional structure of a typical bulk N-channel MOSFET. In the MOSFET shown in
FIG. 21
, a source
2
and a drain
3
are formed at one main surface of a semiconductor substrate
1
. A gate electrode
5
is formed between source
2
and drain
3
on substrate
1
with a gate insulating film
4
interposed therebetween. Substrate
1
and source
2
are connected to ground, and a drain voltage Vd is applied to drain
3
and a gate voltage Vg is applied to gate electrode
5
.
In such bulk MOSFET, flow of electrons “e” through the channel region from source
2
to drain
3
may cause impact ionization as indicated by a star near drain
3
. Impact ionization produces pairs of hole “h” and electron “e” which is the hot carrier with high energy. Holes “h” diffuse in substrate
1
and leave substrate
1
as substrate current Isub through a substrate electrode (or a well electrode). Substrate current Isub can be measured with an ammeter A as shown in FIG.
21
.
Meanwhile, electrons “e” or hot carriers penetrate into gate insulating film
4
, where they may be trapped or produce an interface state between the channel region and the gate insulating film. Such hot carriers degrade the transistor characteristics.
As can be seen from the foregoing, there is a close correlation between the substrate current and hot carriers since the substrate current is generated by hot carriers produced due to impact ionization in the vicinity of the drain. Therefore, the lifetime of a transistor degraded by hot carriers can be estimated by measuring the substrate current.
FIG. 22
schematically shows a cross sectional structure of a typical SOI-MOSFET. In this SOI-MOSFET, a buried insulating layer
6
and a semiconductor layer
1
A are stacked on semiconductor substrate
1
in this order. In the SOI-MOSFET, semiconductor layer
1
A is isolated from substrate
1
by buried insulating layer
6
and semiconductor layer
1
A corresponds to substrate
1
in the bulk MOSFET shown in FIG.
21
. Source
2
and drain
3
are formed in semiconductor layer
1
A. The region of semiconductor layer
1
A excluding source
2
and drain
3
is called a body region
1
B. Between source
2
and drain
3
, gate electrode
5
is formed on semiconductor layer
1
A with gate insulating film
4
interposed therebetween. Source
2
is connected to ground, drain voltage Vd is applied to drain
3
and gate voltage Vg is applied to gate electrode
5
.
As apparent from
FIG. 22
, generally there is no such thing as a substrate electrode in an SOI-MOSFET. Therefore, in general the lifetime of a transistor degraded by hot carriers cannot be estimated from the substrate current.
It is also understood from
FIG. 22
that holes “h” produced by impact ionization tend to accumulate in body region
1
B, since body region
1
B is isolated from substrate
1
by buried insulating layer
6
, thereby increasing the potential of the body region. Increase in potential in body region
1
B turns on an NPN bipolar transistor formed by source
2
, body region
1
B and drain
3
, thereby further increasing the current between source
2
and drain
3
(parasitic bipolar effect). The current increased by such parasitic bipolar effect leads to an increase in production of hot carriers to accelerate degradation in transistor characteristics. Thus, such parasitic bipolar effect also makes it difficult to estimate the lifetime of an SOI-MOSFET degraded by hot carriers.
FIG. 23
is a graph showing the results obtained by measuring the lifetime of the SOI-MOSFET as shown in FIG.
22
. In this graph, the reciprocal 1/Vd(1/V) of the drain current is represented on the horizontal axis and the lifetime &tgr;(sec) of the transistor is represented on a log scale on the vertical axis. The measured SOI-MOSFET has a channel length L of 0.3 &mgr;m and gate voltage Vg of 0.7V is applied thereto as the hot carrier stress condition. As can be seen from
FIG. 23
, the lifetime of the transistor sharply declines in the region with greater drain voltage Vd (the left region of the graph). Thus, since plotting of the transistor lifetime does not result in a straight line, accurate estimation of the lifetime of the SOI-MOSFET is difficult. For example, drain voltage Vd allowed for the SOI-MOSFET to have the lifetime of ten years is 3.13V or lower if estimated from the two leftmost measurement points in the graph, but is 1.96V or lower if estimated from the four measurement points on the right side of the graph. Although plotting of the transistor lifetime presents in good linearity in the region with a relatively small drain voltage, measurement of the transistor lifetime in such region requires a long stress test of approximately 10
4
-10
6
seconds, preventing achievement of a simple lifetime estimation method.
SUMMARY OF THE INVENTION
In view of the problems as described above, an object of the present invention is to provide a method of estimating the lifetime of a floating SOI-MOSFET simply and accurately.
The method of estimating the lifetime of a floating SOI-MOSFET includes the steps of:
deriving, corresponding to at least two stress conditions S
1
and S
2
, substrate currents Isub
1
and Isub
2
, drain currents Id
1
t
and Id
2
t
, and transistor lives &tgr;
1
t
and &tgr;
2
t
from hot carrier stress test for a body-fixed SOI-MOSFET;
using at least Isub
1
, Isub
2
, Id
1
t
, Id
2
t
, &tgr;
1
t
and &tgr;
2
t
to determine constants A and B in the following equation (2)
τ
t
·
Id
t
W
t
=
A
(
Isub
Id
t
)
-
B
(
2
)
which equation includes a channel width W
t
of the body-fixed SOI-MOSFET;
deriving, from measurement, stress condition dependency Isub(S) of the substrate current and stress condition dependency Id
t
(S) of the drain current for the body-fixed SOI-MOSFET, and deriving, from measurement, stress condition dependency Id
f
(S) of the floating SOI-MOSFET; and
using A, B, Isub(S), Id
t
(S), and Id
f
(S) to calculate a lifetime &tgr;
f
(S) of the floating SOI-MOSFET under arbitrary stress conditions from the following equation (5)
τ
f
(
S
)
=
A
·
W
f
1
Id
f
(
S
)
(
Isub
(
S
)
Id
t
(
S
)
)
-
B
(
5
)
which equation includes the known channel width W
f
of the floating SOI-MOSFET.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4816753 (1989-03-01), Palkuti
patent: 5196354 (1993-03-01), Ohtaka et al.
patent: 5608338 (1997-03-01), Maeda
Ong et al., “Hot-Carrier-Induced Degradation in p-MOSFET's Under AC Stress”, IEEE Electron Device Letters, vol. 9, No. 5, May 1988, pp. 211-213.
Kuo et al., “Simulation of MOSFET Lifetime under AC Hot-Electron Stress”, IEEE Trans. on Electron Devices, vol. 35, No. 7, Jul. 1988, pp. 1004-1011.
Werner Weber, “Dynamic Stress Experiments for Understanding Hot-Carrier Degradation Phenomena”, IEEE Trans. on Electron Devices, vol. 35, No. 9, Sep. 1988, pp. 1476-1486.
Ong et al., “p-MOSFET Gate Current and Device Degradation”, 27th Annual Proceedings on Reliability Physics 1989, Apr. 1989, pp. 178-182.
Ong et al., “p-MOSFET Gate Current and Device Degradation”, 1989 Intnl. Symposium on VLSI Technology, Systems, and Applications, May 1989, pp. 193-196.
Mistry et al., “An Empirical Model for the LeffDependence of Hot-Carrier Lifetimes of n-Channel MOSFET's”, IEEE Electron Device Letters, vol. 10, No. 11, Nov. 1989, pp. 500-502.
Bell
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Stamber Eric W.
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