Excavating
Patent
1978-12-06
1983-03-22
Atkinson, Charles E.
Excavating
364200, 370 43, G06F 1110
Patent
active
043778623
ABSTRACT:
Error control, in the form of a modulo 2 division remainder checksum is added to a packet of reformatted asynchronous characters prior to transmission over a data link connecting two data devices such as a host computer and a teletype terminal. At one end of the link, data in asynchronous form, such as ASCII code, comprising seven data bits, start and stop bits, and a parity bit, is originated by one data device. The start, stop and parity bits of each character are eliminated. The remaining data bits for a selected number of characters are then grouped together to form a data grouping and the checksum and other control information bits added, forming an information packet. The information packet is then divided into sections or groups of eight bits. Start and stop bits are added to each group, forming ten bit characters. The ten bit characters are then transmitted over the data link in standard asynchronous format. The process is carried out in reverse at the other end of the link, resulting in the other data device receiving the data in the form originated by the first data device. Sophisticated error control techniques thus may be implemented in asynchronous communications without detrimentally affecting the data capacity of the channel.
REFERENCES:
patent: 3412380 (1968-11-01), Heller et al.
patent: 3646518 (1972-02-01), Weinstein
patent: 3742145 (1973-06-01), Clark et al.
patent: 3805234 (1974-04-01), Masters
patent: 3820083 (1974-06-01), Way
patent: 3825899 (1974-07-01), Haeberle et al.
patent: 3868631 (1975-02-01), Morgan et al.
patent: 3975712 (1976-08-01), Hepworth et al.
patent: 4019172 (1977-04-01), Srodes
patent: 4064370 (1977-12-01), Coonce et al.
patent: 4079452 (1978-03-01), Larson et al.
patent: 4082922 (1978-04-01), Chu
patent: 4126764 (1978-11-01), Downey et al.
Breslau et al., Cyclic Redundancy Check for SDLC Architecture, IBM Technical Disclosure Bulletin, vol. 19, No. 6, Nov. 1976, pp. 2098-2099.
Williams, Developments in Data Communications, Post Office Electrical Engineers Journal, vol. 64, No. 2, Jul. 1971, pp. 70-80.
Schwartz et al., Terminal-Oriented Computer-Communication Networks, Proceeding on the IEEE, vol. 60, No. 11, Nov. 1972, pp. 1408-1423.
S. B. Cooper, Hardware Considerations for High Level Data Link Control Communication, Computer Design, vol. 14, No. 3, Mar. 1975, pp. 81-87.
Jensen William C.
Koford James S.
Woo Barry B.
Atkinson Charles E.
Pursel David G.
The Boeing Company
LandOfFree
Method of error control in asynchronous communications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of error control in asynchronous communications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of error control in asynchronous communications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1872234