Method of erasing nonvolatile tunneling injector memory cell

Details Method of erasing nonvolatile tunneling injector memory cell Method of erasing nonvolatile tunneling injector memory cell

2002-04-29

2003-06-17

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C257S214000, C257S316000

Reexamination Certificate

active

06580642

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to nonvolatile memory devices, and more particularly to a novel method of erasing a negatively charged floating gate of an MOS nonvolatile tunneling injector memory cell.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art.
One such non-volatile memory cell has been proposed in U.S. Published application Ser. No. 2001/0019151 A1, which is hereby incorporated by reference. The tunneling injector memory cell
1
is programmed and erased by injection of electrons and holes respectively on the floating gate. The basic cell structure is shown in
FIGS. 1A and 2A
, and includes a floating gate
10
disposed over and insulated from a substrate
11
by a gate insulation layer
12
. A grid electrode
13
is disposed over the floating gate
10
, and an injector electrode
14
is disposed over the grid electrode
13
. The grid electrode
13
and floating gate
10
are insulated from each other by a retention insulator layer
15
disposed therebetween. Likewise, injector electrode
14
and grid electrode
13
are insulated from each other by a grid insulator layer
16
disposed therebetween. Source and drain regions
17
/
18
are formed in the substrate
11
, defining a channel region
19
therebetween above which the floating gate
10
is disposed.
The programming of the memory cell is illustrated in
FIGS. 1A
, and
1
B. When injector electrode
14
is negatively biased with respect to the grid electrode, electrons will tunnel from the injector electrode to the grid electrode
13
. When this negative bias is increased beyond a certain value (e.g. −3.8 V), some of the electrons will reach the interface between the grid electrode
13
and the retention insulator
15
with enough energy to surmount the energy barrier of the retention insulator
15
. When the potential of the floating gate
10
is positive with respect to the grid electrode potential (i.e. by about 0.5 to 1.0 V), most of the electrons that surmount the energy barrier of the retention insulator
15
will be collected on the floating gate
10
. In this manner, the floating gate is negatively charged. Example potentials of −2V (applied to the injector electrode
14
), +2V (applied to the grid electrode
13
) and +2V (applied to the source/drain regions
17
/
18
) are illustrated in
FIG. 1A
for negatively charging the floating gate
10
.
The erasure of the memory cell is illustrated in
FIGS. 2A and 2B
, which is essentially done by reversing the polarity of the potentials applied to the memory cell electrodes. Specifically, when injector electrode
14
is positively biased with respect to the grid electrode, electrons will tunnel from the grid electrode
13
to the injector electrode
14
. When this positive bias is increased beyond a certain value, holes from the injector electrode
14
have enough energy to surmount the grid insulation layer
16
. When the potential of the floating gate
10
is negative with respect to the grid electrode potential (i.e. by about 0.5 to 1.0 V), the injected holes are collected on the floating gate
10
. In this manner, the negative charge on the floating gate is neutralized. Example potentials of +2.5V (applied to the injector electrode), −2.5V (applied to the grid electrode
13
) and −4V (applied to the source/drain regions
17
/
18
and substrate
11
) are illustrated in
FIG. 2A
for erasing the negative charge on the floating gate
10
.
The material used for the grid electrode
13
can be silicon (e.g. polysilicon or in amorphous form) or other conductive materials (such as tungsten). Polysilicon is illustrated in
FIG. 2
due to its well proven yieldability, manufacturability, and compatibility with state of the art IC technology. In the above described erasure method, the injection efficiency (i.e. the fraction of holes injected from the injector electrode
14
that reach the floating gate
10
) is expected to be between 0.01% to 0.1%. Moreover, approximately 1 million electrons are needed to tunnel to the injector electrode
14
in order to get each hole injected onto the floating gate
10
. A relatively high electrical current between the grid electrode
13
and the injector electrode
14
is therefore needed to inject a significant number of holes onto the floating gate
10
. Thus, the high electron current places a practical limit on the injection of holes onto the floating gate.
There is a need for an erasure method for a tunneling injector memory cell that does not necessitate a high electron current in order to erase negative charges from the floating gate.
SUMMARY OF THE INVENTION
The present invention solves the aforementioned problem by providing an erasure method that does not employ a high grid electrode electrical current to erase the negative charge from the floating gate of a tunneling injector non-volatile memory cell.
The present invention is a method of operating a non volatile memory cell having a floating gate disposed over and insulated from a semiconductor substrate by a gate insulation layer, a grid electrode disposed over and insulated from the floating gate, and an injector electrode disposed over and insulated from the grid electrode, wherein the substrate includes source and drain regions that define a channel region of the substrate therebetween. The method comprising the steps of applying a first voltage to the substrate, and applying a second voltage to at least one of the grid electrode and the injector electrode. The first voltage is sufficiently more positive with respect to the second voltage to induce electrons on the floating gate to tunnel through the gate insulation layer to the substrate via Fowler-Nordheim tunneling.
Another aspect of the present invention is a method of operating a non volatile memory cell having a floating gate disposed over and insulated from a semiconductor substrate by a gate insulation layer, a grid electrode disposed over and insulated from the floating gate, and an injector electrode disposed over and insulated from the grid electrode, wherein the substrate includes source and drain regions that define a channel region of the substrate therebetween. The method comprising the steps of programming the memory cell and erasing the memory cell. Programming the memory cell includes the stops of applying a first voltage to the injector electrode, and applying a second voltage to the grid electrode, wherein the second voltage is sufficiently more positive relative to the first voltage to induce electrons to be injected from the injector electrode, through the grid electrode, and onto the floating gate. Erasing the memory cell includes the steps of applying a third voltage to the substrate, and applying a fourth voltage to at least one of the grid electrode and the injector electrode, wherein the third voltage is sufficiently more positive with respect to the fourth voltage to induce electrons on the floating gate to tunnel through the gate insulation layer to the substrate via Fowler-Nordheim tunneling.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.


REFERENCES:
patent: 6449189 (2002-09-01), Mihnea et al.
patent: 2001/0019151 (2001-09-01), Caywood

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