Method of erasing non-volatile semiconductor memory device...

Details Method of erasing non-volatile semiconductor memory device... Method of erasing non-volatile semiconductor memory device...

2005-03-22

2005-03-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Floating gate

Disturbance control

C365S185240, C365S185260, C365S185290

Reexamination Certificate

active

06870765

ABSTRACT:
A method of erasing a non-volatile semiconductor memory device comprising, to raise the convergence of the erasure voltage, performing a write-erase operation, at least one write-erase operation after erasure, or a plurality of write-erase operations as an operation when erasing a memory transistor including dispersed charge storing means in a gate insulating film interposed between a channel-forming region of the semiconductor and a gate electrode and, to increase the erasure speed, optimizing an erasure voltage and/or an erasure time in accordance with the phenomenon of the absolute value of a voltage of an inflection point taking an extremum at the erasing side in a hysteresis curve shown the change of threshold voltage with respect to an applied voltage of the memory transistor becoming larger along with a shortening of a voltage application time.

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patent: 6011725 (2000-01-01), Eitan
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patent: 6282123 (2001-08-01), Mehta
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patent: 6324099 (2001-11-01), Iijima
patent: 6400610 (2002-06-01), Sadd

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