Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-09-18
2004-04-06
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290
Reexamination Certificate
active
06717860
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of erasing a non-volatile semiconductor memory device having dispersed charge storing means (for example charge traps in a nitride film in a metal-oxide-nitride-oxide-semiconductor (MONOS) type and metal-nitride-oxide-semiconductor (MNOS) type, charge traps near the interface between a top insulating film and a nitride film, or fine particle conductors, etc.) inside a gate insulating film between a channel-forming region and a gate electrode of a memory transistor and performing, as its basic operation, injection of charges (electrons or holes) to the dispersed charge storing means for storage or withdrawing of the same and a such a non-volatile semiconductor memory device.
2. Description of the Related Art
Non-volatile semiconductor memories include, for example, the FG type wherein charge storing means (floating gate ) for holding charges is made planarly and, also, the MONOS type wherein charge storing means (charge traps) are made planarly disperse.
In an FG type non-volatile memory transistor, a floating gate comprised of polyorystalline silicon etc. is stacked on a channel-forming region of a semiconductor via a gate insulating film. A control gate is further stacked on the floating gate via an inter-gate insulating film comprised of an oxide-nitride-oxide (ONO) film etc.
On the other hand, in a MONOS type non-volatile memory transistor, a tunnel insulating film comprised for example of a silicon oxide film, an oxynitride film, etc., an interlayer Insulating film comprised of a nitride film, oxynitride film, etc., and a top insulating film comprised of a silicon oxide film are successively stacked on the channel-forming region of the semiconductor. A gate electrode is formed on the top insulating film.
In a MONOS type non-volatile semiconductor memory, carrier traps serving mainly for holding charges in the nitride film (Si
x
N
y
(0<x<1, 0<y<1)) or at an interface between the top insulating film and the nitride film are discretely dispersed spatially (that is, in the planar direction and film thickness direction), so the charge holding characteristic depends on the energy and spatial distribution of the charge captured by the carrier trap in the Si
x
N
y
film in addition to the tunnel insulating film thickness.
When a leakage current path locally occurs in the tunnel Insulating film, in the FG type, much of the charge passes through the leakage path and the charge holding characteristic is liable to decline, while in the MONOS type, since the charge storing means are spatially dispersed, the local charges around the leakage path pass through the leakage path and only locally leaks and therefore the charge holding characteristic of the overall memory device is resistant to decline.
Therefore, in the MONOS type, the problem of the decline of the charge holding characteristic caused by a tunnel insulating film becoming thinner is not as serious as in the FG type. Accordingly, the MONOS type is superior to the FG type in scaling of the tunnel oxide film in a fine memory transistor having an extremely short gate length.
In the above FG type non-volatile memory or MONOS type or other non-volatile memory where the charge storing means of the memory transistors are planarly dispersed, to reduce the cost per bit, increase the integration, and realize a large scale non-volatile memory, it is essential to realize a one-transistor type cell structure.
However, particularly in a MONOS type or other non-volatile memory, the mainstream is a two-transistor type wherein a selection transistor is connected to a memory transistor. Various studies are currently underway for establishing the one-transistor cell technique.
To establish the one-transistor cell technique, improvement of the disturb characteristic is necessary in addition to optimization of the element structure such as the gate insulating film including the charge storing means and improvement of the reliability. As one means for improving the disturb characteristic of a MONOS type non-volatile memory, studies are being conducted to set the tunnel insulating film thicker than the normal film thickness of 1.6 nm to 2.0 nm.
In a one-transistor cell, since there is no selection transistor in the cell, it is important to reduce the disturb characteristic of the memory transistor in non-selected cells connected to the same common line as a cell to be written in. The technique has already been proposed of applying an inhibit voltage to a source impurity region or drain impurity region of a non-selected memory transistor via a bit line or a source line at the time of writing or reading and thereby preventing erroneous writing and erroneous erasure of the non-selected memory transistor.
Summarizing the problems to be solved by the invention, in a MONOS or other non-volatile semiconductor memory with dispersed charge storing means, however, when the tunnel insulating film is made relatively thick in order to improve the disturb characteristic at the time of programming or a read operation, the erasure speed becomes relatively slow compared with the write speed. As a typical value, compared with a write speed of 0.1 to 1.0 msec, the erasure speed is 80 to 100 msec or two orders slower.
As another problem, in a non-volatile semiconductor memory, in block erasure, the cells in the write state and the cells in the erase state are simultaneously erased. If cells in the erase state are further erased at this time, there is the problem that the threshold voltage of part of the memory cells will become lower than the threshold voltage of the other memory cells due to excess erasing. This lowering of the threshold voltage causes an increase of the leakage current from the non-selected cells at the time of a read operation.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of erasing a non-volatile semiconductor memory device capable of aligning both memory transistors in the erase state and memory transistors in the write state at a constant erased level.
Another object of the present invention is to provide a non-volatile semiconductor memory device having a structure suited for increasing an erasure speed of a MONOS or other memory transistor having a planarly dispersed charge storing means.
To achieve the first object, according to a first aspect of the present invention, there is provided a method of erasing a non-volatile semiconductor memory device having a memory transistor comprising a source region and a drain region formed on a surface portion of a semiconductor while sandwiching a channel-forming region there between, a gate insulating film provided on the channel-forming region and including dispersed charge storing means, and a gate electrode on the gate insulating film, the method comprising the steps of repeating a write-erase operation a plurality of times when erasing the memory transistor.
The method of erasing a non-volatile semiconductor memory device according to a second aspect of the present invention comprises, the steps of: performing an erase operation; and performing a write-erase operation at least once.
The method of erasing the non-volatile semiconductor memory device according to a third aspect of the present invention comprises, when erasing the memory transistor, the steps of: performing a write operation; and performing an erase operation.
The present invention is suitable for a separated source line NOR type and a NOR type non-volatile memory device with source lines and bit lines formed into hierarchies.
Further, concerning the memory transistor structure, the present invention is particularly suited to a MONOS type, a fine particle type having nanocrystals or other small size conductors, and other non-volatile memory transistors having the dispersed charge storing means formed to be dispersed at least in a surface direction facing the channel-forming region. These non-volatile memory transistors having planarly dispersed charge storing means are excellent in scaling o
Depke Robert J.
Holland & Knight LLP
LandOfFree
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