Method of erasing information in non-volatile semiconductor...

Details Method of erasing information in non-volatile semiconductor... Method of erasing information in non-volatile semiconductor...

2005-05-10

2005-05-10

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S218000

Reexamination Certificate

active

06891760

ABSTRACT:
A potential of −3V is applied to a control gate electrode, a potential of 5V is applied to a pair of impurity regions and a potential of 3V is applied to a semiconductor substrate in a non-volatile semiconductor memory device. Accordingly, electrons existing on one impurity region side in a silicon nitride film move toward that impurity region, and electrons existing on the other impurity region side move toward that impurity region. Furthermore, electrons existing in that part (middle part) of the silicon nitride film which is positioned immediately above a region approximately at the middle point between one impurity region and the other impurity region move toward the semiconductor substrate. Therefore, MPE (Miss Placed Electron) is no longer caused in the non-volatile semiconductor memory device.

REFERENCES:
patent: 6469343 (2002-10-01), Miura et al.
patent: 6596590 (2003-07-01), Miura et al.
patent: 6649542 (2003-11-01), Miura et al.
patent: 2001-110918 (2001-04-01), None
patent: 2001-156272 (2001-06-01), None

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