Method of erasing information in memory cells

Details Method of erasing information in memory cells Method of erasing information in memory cells

1993-09-20

1995-06-06

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365200, 365201, 365218, 365900, 257316, G11C 1140

Patent

active

054228433

ABSTRACT:
A method of this invention is applied to a nonvolatile memory device composed of first memory cells connected to one of a first word-line pair and second memory cells connected to the other of the first word-line pair, and a single source shared by the first memory cells and the second memory cells. First, a positive potential of, for example, 5 V is applied to the source, a negative potential of, for example, -10 V is applied to the one of the word-line pair, and the ground potential to the other of the word-line pair. This permits electrons to move from the floating gate of the first memory cells into the source, with the result that the erasing of information is achieved. Next, the positive potential is applied to the source, the negative potential is applied to the other of the word-line pair, and the ground potential to the one of the word-line pair. This permits electrons to move from the floating gates of the second memory cells into the source, with the result that the erasing of information is achieved.

REFERENCES:
patent: 4949309 (1990-08-01), Rao
patent: 5058068 (1991-10-01), Costabello
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5134449 (1992-07-01), Gill et al.
patent: 5185718 (1993-02-01), Ringerson et al.

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