Method of erasing data in nonvolatile semiconductor memory devic

Details Method of erasing data in nonvolatile semiconductor memory devic Method of erasing data in nonvolatile semiconductor memory devic

1998-09-15

1999-11-23

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518527, 365218, G11C 1600

Patent

active

059912057

ABSTRACT:
In a data erase operation of the present invention, a drain terminal is opened. A negative voltage of about -10 V and a voltage of about 5 V are applied to a cell gate and a source terminal, respectively. The voltage of about 1-2 V is applied to a P well terminal and an N well terminal. A ground potential is provided to a substrate. A voltage which is lower than the voltage of the source terminal and higher than the substrate voltage (ground voltage) is applied to a P well and an N well between a source diffusion layer and the substrate. Thus, an electric field generated between a source and a floating gate realizes the erase by means of F-N tunneling.

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patent: 5521866 (1996-05-01), Akaogi
patent: 5770963 (1998-06-01), Akaogi et al.
patent: 5790460 (1998-08-01), Chen et al.
patent: 5818756 (1998-10-01), Sakui et al.
patent: 5838618 (1998-11-01), Lee et al.

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