Method of erasing an NVM cell that utilizes a gated diode

Details Method of erasing an NVM cell that utilizes a gated diode Method of erasing an NVM cell that utilizes a gated diode

2011-06-28

2011-06-28

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185260, C365S185270

Reexamination Certificate

active

07969790

ABSTRACT:
A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time.

REFERENCES:
patent: 5907171 (1999-05-01), Santin et al.

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