Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-10-26
2002-12-03
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185270
Reexamination Certificate
active
06490205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of non-volatile memory devices. More particularly, the invention relates to a method of erasing multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that utilize the phenomena of hot electron injection to trap charge within a trapping dielectric material within the gate.
2. Discussion of Related Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor EEPROM devices involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM.
An example of a single transistor Oxide-Nitrogen-Oxide (ONO) EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memory cell is programmed by hot electron injection and the injected charges are stored in the oxide-nitrideoxide (ONO) layer of the device. This article teaches programming and reading in the forward direction. Thus, a wider charge trapping region is required to achieve a sufficiently large difference in threshold voltages between programming and reading. This, however, makes it much more difficult to erase the device.
An attempt to improve the erasure of such ONO EEPROM devices is disclosed in both U.S. Pat. No. 5,768,192 and PCT patent application publication WO 99/07000, the contents of which are hereby incorporated herein by reference. In those disclosed devices, a cell is erased by applying a constant negative voltage to the gate over a plurality of cycles. However, the efficiency of such erasure is often inadequate since the number of hot electrons created during the erasure cycle is too low.
SUMMARY OF THE INVENTION
One aspect of the invention regards a method of erasing a memory cell with a substrate having a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across said the region. A third constant voltage is applied in a region of the substrate outside of the first and second regions so that a first portion of the first amount of charge is removed from the charge trapping region.
Each of the above aspects of the present invention provides the advantage of improving the efficiency of erasing by increasing the number of hot holes that participate in the erasure process.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.
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Sunkavalli Ravi S.
Wang Janet S. Y.
Amin & Turocy LLP
Ho Hoai
LandOfFree
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