Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-06-04
2003-03-18
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S218000, C365S185240, C365S185250
Reexamination Certificate
active
06535432
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method of erasing a non-volatile memory, and more particularly, to a method of erasing an electrically erasable and programmable read-only memory (EEPROM).
2. Description of the Prior Art
A flash EEPROM device is composed of a large number of memory cells. Each memory cell comprises a floating gate for storing charges which represent data. After the floating gate of the memory cell is charged, the threshold voltage of the memory cell is lifted, so the charged memory cell will not be in a conductive state during addressing in reading. A state of not conducting is regarded as a “0” state by detecting circuits utilizing a binary system. Uncharged memory cells will be regarded as being in a “1” state. The floating gate is charged by utilizing the Fower-Nordheim tunneling mechanism. In this method, the floating gate is discharged, or erased, by forming a high potential between the control gate and the substrate, which transverse the tunneling oxide layer and produce a high electric field, so that negative charges trapped in the floating gate are sucked out and complete erasing.
Please refer to FIG.
1
.
FIG. 1
is a cross-sectional view of memory cells
137
and
138
in a non-volatile memory according to the prior art. The prior art non-volatile memory is positioned on a semiconductor wafer
110
. The semiconductor wafer
110
comprises a semiconductor area
112
. The two memory cells
137
,
138
are positioned on the semiconductor area
112
. A field oxide layer
120
is positioned on the semiconductor area
112
between the memory cells
137
,
138
. The semiconductor area
112
can be a P-type substrate, or a P-type well positioned in the P-type substrate and isolated by an N-type well.
The memory cells
137
,
138
comprise drains
113
,
114
and sources
115
,
116
positioned in the semiconductor area
112
, respectively. Channels
117
,
118
are positioned between the drains
113
,
114
and the sources
115
,
116
, respectively. Tunneling oxide layers
121
,
122
are positioned on the channels
117
,
118
, respectively. Floating gates
123
,
124
are positioned on the tunneling oxide layers
121
,
122
, respectively. Isolating oxide layers
125
,
126
are positioned on the floating gates
123
,
124
, and control gates
127
,
128
are positioned on the isolating oxide layers
125
,
126
, respectively. Terminal
130
provides a substrate voltage Vsub to the semiconductor area
112
. Terminals
131
,
132
provide a gate voltage Vg to the control gates
127
,
128
, respectively.
While performing an optional erasing of the non-volatile memory, such as erasing charges stored in the floating gate
123
of the memory cell
137
, but not erasing the memory cell
138
, the prior art method floats the drains and sources of all of the memory cells. Then, a negative potential(such as −10 volts) is supplied from the terminal
131
to the control gate
127
of the memory cell
137
to be erased. The terminal
132
is grounded in order to supply a relative lower potential (0 V) to the control gate
128
of the memory cell
138
not to be erased. The terminal
130
supplies a positive potential(such as +10 V) to the semiconductor area
112
. Therefore, a potential difference which transverses the tunneling oxide
121
is formed between the control gate
127
and the semiconductor area
112
, and makes negative charges stored in the floating gate
123
accumulate toward the channel
117
. Furthermore, the negative charges in the floating gate
123
are sucked to the channel
117
, as a result of the Fowler-Nordheim tunneling mechanism, to complete the erasing.
When performing the optional erasing mentioned above, a substrate disturbance problem will occur. The memory cell
138
is not erased, so that the threshold voltage of the memory cell
138
does not change before and after the erasing of the memory cell
137
. Detection circuits will regard the memory cell
138
as not in a conductive state when subsequently performing reading, that is, the detection circuits detect the “0” state, as described in the binary system. However, a high positive potential (such as 10 V) supplied to the semiconductor area
112
from the terminal
130
forms a potential difference between the control gate
128
of the memory cell
138
and the semiconductor area
112
, which transverses the tunneling oxide layer
122
, and causes some of the negative charges stored in the floating gate
124
to be sucked into the channel
118
. Therefore the threshold voltage of the memory cell
138
is lowered, so that the memory cell
138
can be regarded as being in a conductive state by the detective circuits during the addressing in reading, and regarded as being in the “1” state described in the binary system.
Since the above-mentioned substrate disturbance problem occursing in the optional erasing mainly results from the memory cells being made in the same semiconductor area
112
, today the memory cells are made in different semiconductor areas when manufacturing the non-volatile memory, in order to resolve the above problem. Please refer to FIG.
2
.
FIG. 2
is the cross-sectional view of memory cells
167
,
168
of another non-volatile memory according to the prior art. The non-volatile memory is positioned on a semiconductor wafer
140
. The semiconductor wafer
140
comprises a substrate
142
, two P-type wells
163
,
164
positioned in the substrate
142
, and two memory cells
167
,
168
positioned on the P-type wells
163
,
164
, respectively.
The memory cells
167
,
168
comprise drains
143
,
144
and sources
145
,
146
positioned in the P-type wells
163
,
164
in the substrate
142
, respectively. Channels
147
,
148
are positioned between the drains
143
,
144
and the sources
145
,
146
, respectively. Tunneling oxide layers
151
,
152
are positioned on the channels
147
,
148
. Floating gates
153
,
154
are positioned on the tunneling oxide layers
151
,
152
. Isolating oxide layers
155
,
156
are positioned on the floating gates
153
,
154
, and control gates
157
,
158
are positioned on the isolating oxide layers
55
,
156
. Terminals
159
,
160
supply a well potential Vw to the P-type wells
163
,
164
, respectively. Terminals
161
,
162
supply a gate potential Vg to the control gates
157
,
158
, respectively.
While performing the optional erasing of the above-mentioned non-volatile memory, such as erasing the memory cell
167
, but not erasing the memory cell
168
, the prior art method floats the drains and the sources of all of the memory cells and grounds the terminals
160
,
162
, so that there will be no potential difference between the control gate
158
of the memory cell
168
and the P-type well
164
. The terminal
159
supplies a high positive potential (such as +10 V) to the P-type well
163
, and the terminal
161
provides a high negative potential (such as −10 V) to the control gate
157
of the memory cell
167
to be erased. Therefore, a high electric field which transverses the tunneling oxide
151
will be formed between the control gate
157
and the P-type well
163
, making the negative charges stored in the floating gate
153
accumulate toward the channel
147
. Furthermore, the negative charges in the floating gate
153
are sucked to the channel
147
, as a result of the Fowler-Nordheim tunneling mechanism, to complete the erasing.
Since the memory cell
167
,
168
is made on different P-type wells
163
,
164
respectively, different potentials will be supplied to the memory cells
167
,
168
and the P-type wells
163
,
164
, respectively, when performing the optional erasing, therefore the substrate disturbance problem is resolved. In the above-mentioned optional erasing, the control gate
158
of the memory cell
168
and the P-type well
164
are both grounded, therefore the negative charges stored in the floating gate
154
do not change before and after erasing. That is, the threshold voltage of the memory cell
Ni Ful-Long
Yen Ching-Fang
Hsu Winston
Macronix International Co. Ltd.
Nguyen Viet Q.
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