Method of erasing a flash memory device

Details Method of erasing a flash memory device Method of erasing a flash memory device

2001-06-15

2002-06-18

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185190, C365S185220, C365S185300

Reexamination Certificate

active

06407947

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a method of erasing a flash memory device, and more particularly, to a method of erasing a flash memory device while avoiding an over-erasure problem.
BACKGROUND OF THE INVENTION
A flash memory device performs an erasure operation by the Fowler-Nordheim (F-N) tunneling effect. This causes the efficiency of the memory device to vary based on the properties and thickness of a tunnel oxide film of about 100 Å (angstroms). As a result, its characteristics are not self-limited for a constant time. Therefore, due to changes occurring during various processes, the erasure rates of cells vary. This results in degradation in the characteristic distribution of the cells, that is, the distribution of the threshold voltage of the erased cells is variable.
A method of erasing a conventional flash memory device will now be explained with reference to
FIG. 1. A
pre-programming operation
11
is first performed by which cells in a selected block are programmed to increase the threshold voltages of certain cells before an erasure operation is performed. A verification process
12
is then performed. The pre-programming operation
11
is performed to prevent the phenomenon by which cells are over-erased. Over-erasure occurs when cells having a low threshold voltage after being erased are erased again thereby moving the twice erased cells to a further low threshold voltage.
After the threshold voltage of all of the cells is adjusted, an erasure operation is performed (block
13
). Next, the state of erasure is verified
14
. If the erasure is not sufficient, a series of operations are repeated by which the erasure operation is again performed. After all the cells are erased, and in order to solve the problem of over-erasure in some of the cells having a relatively fast rate of erasure characteristic, a post-programming operation
15
for preventing leakage current from over-erased cells and a verification operation
16
are performed, thus completing the erasure operation of the flash memory device. The programming operation
11
employs a channel hot electron, whereas the post-programming operation
16
employs an avalanche hot electron.
In this erasure method, the internal voltage upon erasure may vary depending on the manufacture process or operation condition, that is, the temperature and operation power supply.
The flash memory device operates from a common single external power supply and uses a charge pump having a step-up circuit for generating a high voltage in order to erase and store information. It stores information by regulating the high voltage internally generated into an adequate voltage.
The gain value of this voltage regulation circuit is dependent upon external factors. As a result, the internal voltage of the voltage regulation circuit is severely variable during erasure. This change of the internal voltage significantly affects the erasure rate of the cells. When the erasure voltage is low, the erasure rate is excessively lowered, thereby degrading the performance of the device. Whereas, when the erasure voltage is high, the erasure rate is rapidly increased, thus causing an over-erasure problem in which cells are over-erased because the erasure process occurs an unnecessary number of times.
As a result, when information is read from a cell, leakage current is generated from neighboring cells which have experienced over-erasure. To program the cell, information indicating an off-cell must be sensed. However, information erroneously indicating an on-cell will be sensed if the leakage current from neighboring, over-erased cells is excessive. When this occurs, erroneous operation of the device is caused.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, a method of erasing a flash memory device is provided. The method comprises the steps of: (a) performing a preprogram operation in a selected sector having at least some cells; (b) adjusting a value in an address counter; (c) performing an erasure operation by applying an erasure pulse voltage to all of the cells; (d) verifying an erasure state of the cells on a per address unit basis; (e) performing a post programming operation if cells corresponding to a last address are erased; (f) if some cells are not erased, erasing all the cells; (g) determining whether a predetermined maximum number of erasure operations has been exceeded; (h) if the predetermined maximum number of the erasure operations has not been exceeded, determining a number of erased cells; (i) if the determined number of erased cells is below a predetermined minimum number of erased cells, increasing a pulse width of the erasure pulse voltage and repeating at least steps (c) through (g); (j) if the determined number of erased cells is more than a predetermined maximum number of erased cells, reducing the pulse width of the erasure pulse voltage and repeating at least steps (c) through (g); (k) if the determined number of erased cells is between the predetermined maximum number of erased cells and the predetermined minimum number of erased cells, repeating at least steps (c) through (g) without changing the width of the erasure pulse voltage; and (l) if the predetermined maximum number of erasure operations has been exceeded, determining that the flash memory device is defective.
In accordance with another aspect of the invention, a method of erasing a flash memory device is provided which includes the steps of: (a) performing a pre-program operation in a selected sector having at least some cells; (b) adjusting a value in an address counter; (c) performing an erasure operation by applying an erasure pulse voltage to all of the cells (d) verifying an erasure state of the cells on a per address unit basis; (e) performing a post programming operation if cells corresponding to a last address are erased; (f) if some cells are not erased, erasing all the cells; (g) determining whether a predetermined maximum number of erasure operations has been exceeded; (h) if the predetermined maximum number of the erasure operations has not been exceeded, determining a number of erased cells; (i) if the determined number of erased cells is below a predetermined minimum number of erased cells, increasing the erasure pulse voltage and repeating at least steps (c) through (g); (j) if the determined number of erased cells is more than a predetermined maximum number of erased cells, reducing the erasure pulse voltage and repeating at least steps (c) through (g); (k) if the determined number of erased cells is between the predetermined maximum number of erased cells and the predetermined minimum number of erased cells, repeating at least steps (c) through (k) without changing the erasure pulse voltage; and (l) if the pre determined maximum number of erasure operations has been exceeded, determining that the flash memory device is defective.


REFERENCES:
patent: 5991206 (1999-11-01), Shin
patent: 6279070 (2001-08-01), Jeong et al.

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